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//
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//
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// Internal wires and regs
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// Internal wires and regs
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//
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//
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reg [5:0] serial_mul_cnt;
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reg [5:0] serial_mul_cnt;
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reg mul_free;
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reg mul_free;
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wire [WIDTH-1:0] x;
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wire [WIDTH-1:0] x;
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wire [WIDTH-1:0] y;
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wire [WIDTH-1:0] y;
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reg ex_freeze_r;
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reg ex_freeze_r;
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always @( posedge clk)
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always @( posedge clk)
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if (reset) ex_freeze_r <= 1'b1;
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if (reset) ex_freeze_r <= 1'b1;
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else ex_freeze_r <= ex_freeze;
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else ex_freeze_r <= ex_freeze;
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//
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//
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// Combinatorial logic
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// Combinatorial logic
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//
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//
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assign x = a_in;
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assign x = a_in;
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assign y = b_in;
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assign y = b_in;
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`ifndef SYNTHESYS
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`ifndef SYNTHESIS
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always@(posedge clk)
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always@(posedge clk)
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if((serial_mul_cnt == 6'b000000) && ex_freeze && ex_freeze_r)
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if((serial_mul_cnt == 6'b000000) && ex_freeze && ex_freeze_r)
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begin
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begin
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$display("%t %m mul (%x,%x,%x);",$realtime,a_in,b_in,mul_prod_r );
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$display("%t %m mul (%x,%x,%x);",$realtime,a_in,b_in,mul_prod_r );
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end
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end
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`endif
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`endif
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always @( posedge clk)
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always @( posedge clk)
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if (reset) begin
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if (reset) begin
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mul_prod_r <= 64'h0000_0000_0000_0000;
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mul_prod_r <= 64'h0000_0000_0000_0000;
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serial_mul_cnt <= 6'd0;
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serial_mul_cnt <= 6'd0;
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mul_free <= 1'b1;
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mul_free <= 1'b1;
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end
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end
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else if (|serial_mul_cnt) begin
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else if (|serial_mul_cnt) begin
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serial_mul_cnt <= serial_mul_cnt - 6'd1;
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serial_mul_cnt <= serial_mul_cnt - 6'd1;
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if (mul_prod_r[0])
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if (mul_prod_r[0])
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mul_prod_r[(WIDTH*2)-1:WIDTH-1] <= mul_prod_r[(WIDTH*2)-1:WIDTH] + x;
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mul_prod_r[(WIDTH*2)-1:WIDTH-1] <= mul_prod_r[(WIDTH*2)-1:WIDTH] + x;
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else
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else
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mul_prod_r[(WIDTH*2)-1:WIDTH-1] <= {1'b0,mul_prod_r[(WIDTH*2)-1: WIDTH]};
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mul_prod_r[(WIDTH*2)-1:WIDTH-1] <= {1'b0,mul_prod_r[(WIDTH*2)-1: WIDTH]};
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mul_prod_r[WIDTH-2:0] <= mul_prod_r[WIDTH-1:1];
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mul_prod_r[WIDTH-2:0] <= mul_prod_r[WIDTH-1:1];
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end
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end
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else if (alu_op_mul && mul_free) begin
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else if (alu_op_mul && mul_free) begin
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mul_prod_r <= {32'd0, y};
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mul_prod_r <= {32'd0, y};
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mul_free <= 0;
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mul_free <= 0;
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serial_mul_cnt <= 6'b10_0000;
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serial_mul_cnt <= 6'b10_0000;
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end
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end
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else if (!ex_freeze | mul_free) begin
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else if (!ex_freeze | mul_free) begin
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mul_free <= 1'b1;
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mul_free <= 1'b1;
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end
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end
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assign mul_stall = (|serial_mul_cnt) | (alu_op_mul & !ex_freeze_r);
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assign mul_stall = (|serial_mul_cnt) | (alu_op_mul & !ex_freeze_r);
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