URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Go to most recent revision |
Only display areas with differences |
Details |
Blame |
View Log
| Rev 133 |
Rev 134 |
|
|
|
-->
|
|
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
xmlns:socgen="http://opencores.org"
|
xmlns:socgen="http://opencores.org"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
|
|
|
opencores.org
|
opencores.org
|
cde
|
cde
|
mult
|
mult
|
generic default
|
generic default
|
|
|
|
|
|
|
|
|
|
|
|
|
elab_verilog
|
|
102.1
|
|
none
|
|
:*Simulation:*
|
|
./tools/verilog/elab_verilog
|
|
|
|
|
|
configuration
|
|
default
|
|
|
|
|
|
dest_dir
|
|
io_ports
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilog
|
gen_verilog
|
104.0
|
104.0
|
none
|
none
|
common
|
common
|
./tools/verilog/gen_verilog
|
./tools/verilog/gen_verilog
|
|
|
|
|
destination
|
destination
|
top.generic
|
mult_generic
|
|
|
|
|
dest_dir
|
|
../verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilogLib_sim
|
gen_verilogLib_sim
|
105.0
|
105.0
|
none
|
none
|
:*Simulation:*
|
:*Simulation:*
|
./tools/verilog/gen_verilogLib
|
./tools/verilog/gen_verilogLib
|
|
|
|
|
dest_dir
|
dest_dir
|
../views
|
../views
|
|
|
|
|
view
|
view
|
sim
|
sim
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
gen_verilogLib_syn
|
gen_verilogLib_syn
|
105.0
|
105.0
|
none
|
none
|
:*Synthesis:*
|
:*Synthesis:*
|
./tools/verilog/gen_verilogLib
|
./tools/verilog/gen_verilogLib
|
|
|
|
|
dest_dir
|
dest_dir
|
../views
|
../views
|
|
|
|
|
view
|
view
|
syn
|
syn
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-common
|
fs-common
|
|
|
|
|
|
|
../verilog/top.generic
|
../verilog/top.generic
|
verilogSourcefragment
|
verilogSourcefragment
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-sim
|
fs-sim
|
|
|
|
|
|
|
../verilog/common/top.generic
|
../verilog/common/mult_generic
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
../verilog/or1200_gmultp2_32x32.v
|
../verilog/or1200_gmultp2_32x32.v
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
|
|
dest_dir../views/sim/
|
dest_dir../views/sim/
|
verilogSourcelibraryDir
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-syn
|
fs-syn
|
|
|
|
|
../verilog/common/top.generic
|
../verilog/common/mult_generic
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
../verilog/or1200_gmultp2_32x32.v
|
../verilog/or1200_gmultp2_32x32.v
|
verilogSourcemodule
|
verilogSourcemodule
|
|
|
|
|
|
|
dest_dir../views/syn/
|
dest_dir../views/syn/
|
verilogSourcelibraryDir
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
fs-lint
|
fs-lint
|
|
|
dest_dir../views/syn/
|
dest_dir../views/syn/
|
verilogSourcelibraryDir
|
verilogSourcelibraryDir
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
commoncommon
|
commoncommon
|
|
|
Verilog
|
Verilog
|
|
|
|
|
fs-common
|
fs-common
|
|
|
|
|
|
|
|
|
sim:*Simulation:*
|
sim:*Simulation:*
|
|
|
Verilog
|
Verilog
|
|
|
|
|
fs-sim
|
fs-sim
|
|
|
|
|
|
|
|
|
|
|
|
|
syn:*Synthesis:*
|
syn:*Synthesis:*
|
|
|
Verilog
|
Verilog
|
|
|
|
|
fs-syn
|
fs-syn
|
|
|
|
|
|
|
|
|
|
|
|
|
doc
|
doc
|
|
|
|
|
spirit:library="Testbench"
|
spirit:library="Testbench"
|
spirit:name="toolflow"
|
spirit:name="toolflow"
|
spirit:version="documentation"/>
|
spirit:version="documentation"/>
|
|
|
:*Documentation:*
|
:*Documentation:*
|
Verilog
|
Verilog
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
clk
|
clk
|
wire
|
wire
|
in
|
in
|
|
|
|
|
reset
|
reset
|
wire
|
wire
|
in
|
in
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
a_in
|
a_in
|
wire
|
wire
|
in
|
in
|
WIDTH-10
|
WIDTH-10
|
|
|
|
|
|
|
b_in
|
b_in
|
wire
|
wire
|
in
|
in
|
WIDTH-10
|
WIDTH-10
|
|
|
|
|
|
|
alu_op_mul
|
alu_op_mul
|
wire
|
wire
|
in
|
in
|
|
|
|
|
|
|
ex_freeze
|
ex_freeze
|
wire
|
wire
|
in
|
in
|
|
|
|
|
|
|
|
|
|
|
mul_prod_r
|
mul_prod_r
|
reg
|
reg
|
out
|
out
|
2*WIDTH-10
|
2*WIDTH-10
|
|
|
|
|
|
|
mul_stall
|
mul_stall
|
wire
|
wire
|
out
|
out
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.