Subversion Repositories socgen

reg [31:0]  a_in_R;

reg [31:0]  a_in_R;

reg [31:0]  b_in_R;

reg [31:0]  b_in_R;

reg [63:0]  mul_prod_exp_R;

reg [63:0]  mul_prod_exp_R;

reg   alu_op_mul_R;

reg   alu_op_mul_R;

reg   ex_freeze_R;

reg   ex_freeze_R;

reg   mask_R;

reg   mask_R;

assign   mul_prod_exp_P =  mul_prod_exp_R;

assign   mul_prod_exp_P =  mul_prod_exp_R;

assign a_in       = a_in_R;

assign a_in       = a_in_R;

assign b_in       = b_in_R;

assign b_in       = b_in_R;

assign alu_op_mul = alu_op_mul_R;

assign alu_op_mul = alu_op_mul_R;

assign ex_freeze  = ex_freeze_R;

assign ex_freeze  = ex_freeze_R;

assign   mask =  {32{mask_R}};

assign   mask =  {32{mask_R}};

  task u_cmp;

  task u_cmp;

    input  [31:0] a_in;

    input  [31:0] a_in;

    input  [31:0] b_in;

    input  [31:0] b_in;

    input  [31:0] exp;

    input  [31:0] exp;

     begin

     begin

      test.a_in_R <= a_in;

      test.a_in_R <= a_in;

      test.b_in_R <= b_in;

      test.b_in_R <= b_in;

      test.mul_prod_exp_R <= exp;

      test.mul_prod_exp_R <= exp;

      test.alu_op_mul_R  <= 1'b1;

      test.alu_op_mul_R  <= 1'b1;

      test.ex_freeze_R    <= 1'b1;

      test.ex_freeze_R    <= 1'b1;

      test.cg.next(1);

      test.cg.next(1);

      while(mul_stall)        test.cg.next(1);

      while(mul_stall)        test.cg.next(1);

      test.mask_R  <= 1'b1;

      test.mask_R  <= 1'b1;

      $display("%t %m   cycle %x %x %x",$realtime,a_in,b_in,exp );

      $display("%t %m   cycle %x %x %x",$realtime,a_in,b_in,exp );

      test.alu_op_mul_R  <= 1'b0;

      test.alu_op_mul_R  <= 1'b0;

      test.ex_freeze_R   <= 1'b0;

      test.ex_freeze_R   <= 1'b0;

      test.cg.next(1);

      test.cg.next(1);

      test.mask_R  <= 1'b0;

      test.mask_R  <= 1'b0;

   end

   end

  endtask

  endtask

`endif

`endif

assign STOP = 1'b0;

assign STOP = 1'b0;

assign BAD = 1'b0;

assign BAD = 1'b0;