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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [pad/] [rtl/] [xml/] [cde_pad_in_dig.xml] - Diff between revs 131 and 134

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Rev 131 Rev 134
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
opencores.org
opencores.org
cde
cde
pad
pad
in_dig  default
in_dig  default
 pad_ring
 pad_ring
  
  
  
  
  
  
    
    
      
      
        PAD_in
        PAD_in
        PAD
        PAD
        
        
      
      
    
    
 
 
 pad
 pad
  
  
  
  
  
  
    
    
      
      
        pad_in
        pad_in
        pad_in
        pad_in
        
        
      
      
    
    
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  gen_verilog
 
  104.0
 
  none
 
  common
 
  ./tools/verilog/gen_verilog
 
  
 
    
 
      destination
 
      pad_in_dig
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
       
       
 
 
 
             
 
              verilog
 
              
 
              
 
                                   spirit:library="Testbench"
 
                                   spirit:name="toolflow"
 
                                   spirit:version="verilog"/>
 
              
 
              
 
 
 
 
 
 
 
              
 
              commoncommon
 
              Verilog
 
              
 
                     
 
                            fs-common
 
                     
 
              
 
 
 
 
              
              
              sim:*Simulation:*
              sim:*Simulation:*
              Verilog
              Verilog
              
              
                     
                     
                            fs-sim
                            fs-sim
                     
                     
              
              
              
              
              syn:*Synthesis:*
              syn:*Synthesis:*
              Verilog
              Verilog
              
              
                     
                     
                            fs-syn
                            fs-syn
                     
                     
              
              
             
             
              doc
              doc
              
              
              
              
                                   spirit:library="Testbench"
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
                                   spirit:version="documentation"/>
              
              
              :*Documentation:*
              :*Documentation:*
              Verilog
              Verilog
              
              
      
      
WIDTH1
WIDTH1
PAD
PAD
wire
wire
in
in
WIDTH-10
WIDTH-10
pad_in
pad_in
wire
wire
out
out
WIDTH-10
WIDTH-10
 
 
 
 
 
 
 
 
 
      fs-common
 
 
 
      
 
        
 
        ../verilog/pad_in_dig
 
        verilogSourcefragment
 
      
 
 
 
   
 
 
 
 
 
 
   
   
      fs-sim
      fs-sim
 
 
 
 
 
   
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
 
 
      
 
        
 
        ../verilog/common/pad_in_dig
 
        verilogSourcemodule
 
      
 
 
 
 
 
 
       
       
        dest_dir
        dest_dir
        ../verilog/
        ../views/sim/
        verilogSourcelibraryDir
        verilogSourcelibraryDir
      
      
  
  
   
   
      fs-syn
      fs-syn
 
 
 
 
 
   
 
        
 
        ../verilog/copyright
 
        verilogSourceinclude
 
      
 
 
 
 
 
      
 
        
 
        ../verilog/common/pad_in_dig
 
        verilogSourcemodule
 
      
 
 
 
 
      
      
        dest_dir
        dest_dir
        ../verilog/
        ../views/syn/
        verilogSourcelibraryDir
        verilogSourcelibraryDir
      
      
   
   
    
    
      fs-lint
      fs-lint
      
      
        dest_dir
        dest_dir
        ../verilog/
        ../views/syn/
        verilogSourcelibraryDir
        verilogSourcelibraryDir
      
      
    
    
 
 

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