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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [verilog/] [lint/] [sram_dp.v] - Diff between revs 131 and 134

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Rev 131 Rev 134
 module
 module
  cde_sram_dp
  cde_sram_dp
    #( parameter
    #( parameter
      ADDR=10,
      ADDR=10,
      WIDTH=8,
      WIDTH=8,
      WORDS=1024,
      WORDS=1024,
      WRITETHRU=0,
      WRITETHRU=0
      DEFAULT={WIDTH{1'b1}},
      )
      INIT_FILE="NONE",
 
      INSTANCE_NAME="U1")
 
     (
     (
 input   wire                 clk,
 input   wire                 clk,
 input   wire                 cs,
 input   wire                 cs,
 input   wire                 rd,
 input   wire                 rd,
 input   wire                 wr,
 input   wire                 wr,
 input   wire    [ ADDR-1 :  0]        raddr,
 input   wire    [ ADDR-1 :  0]        raddr,
 input   wire    [ ADDR-1 :  0]        waddr,
 input   wire    [ ADDR-1 :  0]        waddr,
 input   wire    [ WIDTH-1 :  0]        wdata,
 input   wire    [ WIDTH-1 :  0]        wdata,
 output   reg    [ WIDTH-1 :  0]        rdata);
 output   reg    [ WIDTH-1 :  0]        rdata);
  // Simple loop back for linting and code coverage
  // Simple loop back for linting and code coverage
  always@(posedge clk)
  always@(posedge clk)
        if( rd && cs ) rdata             <= wdata;
        if( rd && cs ) rdata             <= wdata;
        else           rdata             <= DEFAULT;
        else           rdata             <= {WIDTH{1'b1}};
  endmodule
  endmodule
 
 

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