/**********************************************************************/
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/**********************************************************************/
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/* */
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/* */
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/* */
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/* */
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/* Copyright (c) 2012 Ouabache Design Works */
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/* Copyright (c) 2012 Ouabache Design Works */
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/* */
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/* */
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/* All Rights Reserved Worldwide */
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/* All Rights Reserved Worldwide */
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/* */
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/* */
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/* Licensed under the Apache License,Version2.0 (the'License'); */
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/* Licensed under the Apache License,Version2.0 (the'License'); */
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/* you may not use this file except in compliance with the License. */
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/* you may not use this file except in compliance with the License. */
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/* You may obtain a copy of the License at */
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/* You may obtain a copy of the License at */
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/* */
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/* */
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/* http://www.apache.org/licenses/LICENSE-2.0 */
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/* http://www.apache.org/licenses/LICENSE-2.0 */
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/* */
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/* */
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/* Unless required by applicable law or agreed to in */
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/* Unless required by applicable law or agreed to in */
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/* writing, software distributed under the License is */
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/* writing, software distributed under the License is */
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/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */
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/* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */
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/* OR CONDITIONS OF ANY KIND, either express or implied. */
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/* OR CONDITIONS OF ANY KIND, either express or implied. */
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/* See the License for the specific language governing */
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/* See the License for the specific language governing */
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/* permissions and limitations under the License. */
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/* permissions and limitations under the License. */
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/**********************************************************************/
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/**********************************************************************/
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module
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module
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cde_sram_word
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cde_sram_word
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#( parameter
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#( parameter
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ADDR=10,
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ADDR=10,
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WORDS=1024,
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WORDS=1024,
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WRITETHRU=0,
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WRITETHRU=0
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DEFAULT={16'hffff},
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)
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INIT_FILE="NONE")
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(
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(
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input wire clk,
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input wire clk,
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input wire cs,
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input wire cs,
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input wire rd,
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input wire rd,
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input wire wr,
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input wire wr,
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input wire [ ADDR-1 : 0] addr,
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input wire [ ADDR-1 : 0] addr,
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input wire [ 15 : 0] wdata,
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input wire [ 15 : 0] wdata,
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input wire [ 1 : 0] be,
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input wire [ 1 : 0] be,
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output reg [ 15 : 0] rdata);
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output reg [ 15 : 0] rdata);
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always@(posedge clk)
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always@(posedge clk)
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if( rd && cs ) rdata <= wdata ;
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if( rd && cs ) rdata <= wdata ;
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else rdata <= DEFAULT;
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else rdata <= 16'hffff;
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endmodule
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endmodule
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