// Memory Array
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// Memory Array
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reg [WIDTH-1:0] mem[0:WORDS-1];
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reg [WIDTH-1:0] mem [0:WORDS-1];
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// If used as Rom then load a memory image at startup
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// If used as Rom then load a memory image at startup
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initial
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initial
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begin
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begin
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$display("SRAM dp %m.mem");
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$display("SRAM dp %m.mem");
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$display(" AddrBits=%d DataBits = %d Words = %d ",ADDR,WIDTH,WORDS);
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$display(" AddrBits=%d DataBits = %d Words = %d ",ADDR,WIDTH,WORDS);
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end
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end
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// Write function
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// Write function
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always@(posedge clk)
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always@(posedge clk)
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if( wr && cs ) mem[waddr[ADDR-1:0]] <= wdata[WIDTH-1:0];
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if( wr && cs ) mem[waddr[ADDR-1:0]] <= wdata[WIDTH-1:0];
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reg [ADDR-1:0] l_raddr;
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reg [ADDR-1:0] l_raddr;
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reg l_cycle;
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reg l_cycle;
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always@(posedge clk)
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always@(posedge clk)
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begin
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begin
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l_raddr <= raddr;
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l_raddr <= raddr;
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l_cycle <= rd && cs ;
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l_cycle <= rd && cs ;
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end
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end
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generate
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generate
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if( WRITETHRU)
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if( WRITETHRU)
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begin
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begin
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// Read function gets new data if also a write cycle
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// Read function gets new data if also a write cycle
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// latch the read addr for next cycle
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// latch the read addr for next cycle
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// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
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// Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
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wire [WIDTH-1:0] tmp_rdata;
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wire [WIDTH-1:0] tmp_rdata;
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assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}};
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assign tmp_rdata = (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}};
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always@(*) rdata = tmp_rdata;
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always@(*) rdata = tmp_rdata;
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end
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end
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else
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else
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begin
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begin
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// Read function gets old data if also a write cycle
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// Read function gets old data if also a write cycle
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always@(posedge clk)
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always@(posedge clk)
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if( rd && cs ) rdata <= mem[{raddr[ADDR-1:0]}];
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if( rd && cs ) rdata <= mem[{raddr[ADDR-1:0]}];
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else rdata <= {WIDTH{1'b1}};
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else rdata <= {WIDTH{1'b1}};
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end
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end
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endgenerate
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endgenerate
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