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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Diff between revs 131 and 134

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Rev 131 Rev 134
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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
opencores.org
opencores.org
cde
cde
sram
sram
dp  default
dp  default
 
 
 
 
 
 
 
 
 
  gen_verilog
 
  104.0
 
  none
 
  common
 
  ./tools/verilog/gen_verilog
 
  
 
    
 
      destination
 
      sram_dp
 
    
 
  
 
 
 
 
 
 
 
 
 
 
 
 
       
       
              
              
 
              verilog
 
              
 
              
 
                                   spirit:library="Testbench"
 
                                   spirit:name="toolflow"
 
                                   spirit:version="verilog"/>
 
              
 
              
 
 
 
             
 
              commoncommon
 
              Verilog
 
              
 
                     
 
                            fs-common
 
                     
 
              
 
 
 
 
 
              
              sim:*Simulation:*
              sim:*Simulation:*
              Verilog
              Verilog
                     
                     
                            fs-sim
                            fs-sim
                     
                     
              
              
              
              
              syn:*Synthesis:*
              syn:*Synthesis:*
              Verilog
              Verilog
                     
                     
                            fs-syn
                            fs-syn
                     
                     
              
              
              
              
              lintlint
              lintlint
              Verilog
              Verilog
                     
                     
                            fs-lint
                            fs-lint
                     
                     
              
              
              
              
              doc
              doc
              
              
              
              
                                   spirit:library="Testbench"
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
                                   spirit:version="documentation"/>
              
              
              :*Documentation:*
              :*Documentation:*
              Verilog
              Verilog
              
              
      
      
 
 
 
 
 
 
ADDR0
 
WIDTH0
 
WORDS0
 
WRITETHRU0
 
DEFAULT{WIDTH{1'bx}}
 
 
 
 
 
 
 
 
 
 
 
clk
clk
wire
wire
in
in
cs
cs
wire
wire
in
in
wr
wr
wire
wire
in
in
rd
rd
wire
wire
in
in
waddr
waddr
wire
wire
in
in
ADDR-10
ADDR-10
raddr
raddr
wire
wire
in
in
ADDR-10
ADDR-10
wdata
wdata
wire
wire
in
in
WIDTH-10
WIDTH-10
rdata
rdata
reg
reg
out
out
WIDTH-10
WIDTH-10
 
 
 
  
 
      fs-common
 
 
 
      
 
        
 
        ../verilog/sram_dp
 
        verilogSourcefragment
 
      
 
 
   
 
      fs-sim
 
 
 
       
       
        dest_dir../verilog/
        
        verilogSourcelibraryDir
        ../verilog/copyright
 
        verilogSourceinclude
      
      
  
   
   
   
      fs-syn
      fs-sim
 
 
 
 
       
       
        dest_dir../verilog/
        
        verilogSourcelibraryDir
        ../verilog/common/sram_dp
 
        verilogSourcemodule
      
      
 
 
   
       
 
        dest_dir../views/sim/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
 
  
 
 
   
   
      fs-lint
      fs-syn
 
 
 
 
       
       
        dest_dir../verilog/lint/
        
        verilogSourcelibraryDir
        ../verilog/common/sram_dp
 
        verilogSourcemodule
      
      
 
 
   
 
 
 
 
       
 
        dest_dir../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
 
 
 
   
 
 
 
 
 
   
 
      fs-lint
 
 
 
       
 
        dest_dir../views/syn/
 
        verilogSourcelibraryDir
 
      
 
 
 
   
 
 
 
 

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