v 20100214 2
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v 20100214 2
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C 42600 22000 1 0 0 frame_800x600.sym
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C 42300 22100 1 0 0 frame_800x600.sym
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B 49500 27200 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 42400 28400 9 10 1 0 0 0 1
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B 42900 22200 6000 5800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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PROJECT Database
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T 49500 27300 9 10 1 0 0 0 1
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T 42600 28000 9 10 1 0 0 0 1
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Serial Uart
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PROJECT
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T 49500 26700 9 10 1 0 0 0 1
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B 42800 26900 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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VGA Display
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T 42900 27000 9 10 1 0 0 0 1
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T 49600 26200 9 10 1 0 0 0 1
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PROG1
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PS2 Mouse
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T 42700 27300 9 10 1 0 0 0 1
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T 49600 25600 9 10 1 0 0 0 1
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SW
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Switches
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B 42800 26600 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 49700 25100 9 10 1 0 0 0 1
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T 42900 26700 9 10 1 0 0 0 1
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Leds
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PROG2
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T 49500 24500 9 10 1 0 0 0 1
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B 42800 25900 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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Push Buttons
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B 42800 25600 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 49500 23900 9 10 1 0 0 0 1
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T 42900 26000 9 10 1 0 0 0 1
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7 Seg display
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CMP1
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T 49500 23100 9 10 1 0 0 0 1
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T 42700 26300 9 10 1 0 0 0 1
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I/O connectors
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IP
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B 49500 25500 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 42900 25700 9 10 1 0 0 0 1
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B 49500 25000 900 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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CMP2
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B 49500 26600 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 42800 25300 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 49500 26100 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 42900 25400 9 10 1 0 0 0 1
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B 49500 24400 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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CMP3
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B 49500 23800 1100 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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L 44300 28700 44300 22100 3 0 0 0 -1 -1
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B 49500 23000 1200 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 44700 27000 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 43000 28400 9 10 1 0 0 0 1
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B 44700 26700 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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System
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B 44700 26000 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 43100 27600 9 10 1 0 0 0 1
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B 44700 25700 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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PCA (Nexys2)
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B 44700 25400 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 43400 26900 9 10 1 0 0 0 1
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T 44500 28400 9 10 1 0 0 0 1
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Targeted Component (Xilinx Spartan 3E-500 FG320)
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COMPONENT Database
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B 43200 22600 5400 4500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 44500 28000 9 10 1 0 0 0 1
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B 43500 23100 4800 3500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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COMPONENT
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T 43800 26200 9 10 1 0 0 0 1
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T 44800 27100 9 10 1 0 0 0 1
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Padring
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FSM1
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T 44100 25700 9 10 1 0 0 0 1
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T 44600 27400 9 10 1 0 0 0 1
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Core
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FSM
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T 44300 25200 9 10 1 0 0 0 1
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T 44800 26800 9 10 1 0 0 0 1
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Component
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FSM2
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B 43800 23500 4200 2500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 44800 26100 9 10 1 0 0 0 1
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B 44100 23800 3600 1700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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RTL1
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B 44400 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 44600 26400 9 10 1 0 0 0 1
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B 45500 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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VERILOG
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B 46600 24200 800 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 44800 25800 9 10 1 0 0 0 1
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T 44500 24800 9 10 1 0 0 0 1
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RTL2
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comp
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T 44800 25500 9 10 1 0 0 0 1
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T 45600 24800 9 10 1 0 0 0 1
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RTL3
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comp
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B 44700 24600 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 46700 24800 9 10 1 0 0 0 1
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B 44700 24300 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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comp
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B 44700 24000 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 44500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 44800 24700 9 10 1 0 0 0 1
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B 45500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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VAR1
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B 46500 27400 600 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 44600 25000 9 10 1 0 0 0 1
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B 47500 27400 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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VARIANTS
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T 44600 27600 9 10 1 0 0 0 1
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T 44800 24400 9 10 1 0 0 0 1
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IC
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VAR2
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T 45600 27600 9 10 1 0 0 0 1
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T 44800 24100 9 10 1 0 0 0 1
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IC
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VAR3
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T 46600 27600 9 10 1 0 0 0 1
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T 44400 27700 9 10 1 0 0 0 1
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IC
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RTL
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T 47600 27600 9 10 1 0 0 0 1
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B 44500 22400 1500 5200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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IC
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B 42500 22600 1600 5000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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L 48900 27400 49500 27400 3 0 0 0 -1 -1
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B 46600 27000 1500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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L 48900 26800 49500 26800 3 0 0 0 -1 -1
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B 46600 24600 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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L 48900 26300 49500 26300 3 0 0 0 -1 -1
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B 46600 24300 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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L 48900 25700 49500 25700 3 0 0 0 -1 -1
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B 46600 24000 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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L 48900 25200 49500 25200 3 0 0 0 -1 -1
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B 46300 23900 1800 3700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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L 48900 24600 49500 24600 3 0 0 0 -1 -1
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T 46700 27100 9 10 1 0 0 0 1
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L 48900 24000 49500 24000 3 0 0 0 -1 -1
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VAR1_PROG2
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L 48900 23200 49500 23200 3 0 0 0 -1 -1
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T 46500 27400 9 10 1 0 0 0 1
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RUN
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T 46700 26800 9 10 1 0 0 0 1
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VAR2_PROG1
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T 46700 26500 9 10 1 0 0 0 1
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VAR1_TST1
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T 46700 26200 9 10 1 0 0 0 1
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VAR2_TST1
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T 46700 25900 9 10 1 0 0 0 1
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VAR3_TST2
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T 46700 24700 9 10 1 0 0 0 1
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VAR1
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T 46500 25000 9 10 1 0 0 0 1
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COV
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T 46700 24400 9 10 1 0 0 0 1
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VAR2
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T 46700 24100 9 10 1 0 0 0 1
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VAR3
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T 46300 27700 9 10 1 0 0 0 1
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SIM
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B 46600 26700 1500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 46600 26400 1500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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|
B 46600 26100 1500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 46600 25800 1500 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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B 48400 23900 1900 3700 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 48400 27100 9 10 1 0 0 0 1
|
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TRG1_VAR1_PROG2
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T 48400 27700 9 10 1 0 0 0 1
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SYN
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T 48400 26800 9 10 1 0 0 0 1
|
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TRG1_VAR2_PROG2
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T 48400 26500 9 10 1 0 0 0 1
|
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TRG1_VAR3_PROG2
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|
T 48400 26200 9 10 1 0 0 0 1
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TRG2_VAR1_PROG2
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|
T 48400 25900 9 10 1 0 0 0 1
|
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TRG2_VAR2_PROG1
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|
B 42800 24600 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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|
B 42800 24300 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
T 42900 24700 9 10 1 0 0 0 1
|
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TOOL1
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T 42700 25000 9 10 1 0 0 0 1
|
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BIN
|
|
T 42900 24400 9 10 1 0 0 0 1
|
|
TOOL2
|
|
B 44700 23300 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
B 44700 23000 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
|
B 44700 22700 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 44800 23400 9 10 1 0 0 0 1
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VAR1.xml
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|
T 44600 23700 9 10 1 0 0 0 1
|
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XML
|
|
T 44800 23100 9 10 1 0 0 0 1
|
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VAR2.xml
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T 44800 22800 9 10 1 0 0 0 1
|
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VAR3.xml
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B 42800 23500 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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|
B 42800 23200 1000 300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 42900 23600 9 10 1 0 0 0 1
|
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PROGX
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T 42700 23900 9 10 1 0 0 0 1
|
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CHILDREN
|
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T 42900 23300 9 10 1 0 0 0 1
|
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PROGY
|
|
T 46300 23400 9 10 1 0 0 0 1
|
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DOCS
|
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B 46300 22500 2300 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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