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<p><br>
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<p><br>
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<br>
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<br>
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</p>
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</p>
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<h1><a name="socgen_project"></a>SOCGEN Project</h1>
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<h1><a name="socgen_project"></a>SOCGEN Project</h1>
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<h2>Signal,Port and Pad Naming Guidelines</h2>
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<h2>Signal,Port and Pad Naming Guidelines</h2>
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<p><br>
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<p><br>
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<br>
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<br>
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</p>
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</p>
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<p>As designs and design teams continue to grow in size it is mandatory
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<p>As Digital designs and design teams continue to grow it is
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that all rtl code must follow established name space guidelines. The
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mandatory
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days when designers could simply pull names out of thin air are faster
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that all rtl code must follow an established name space guideline. The
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days when designers could simply pull names out of thin air are fast
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disappearing. Naming guidelines have three functions. First they
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disappearing. Naming guidelines have three functions. First they
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ensure that no two designers select the same name for different objects
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ensure that no two designers select the same name for different objects
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and have a name collision. The second function is to ensure that the
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and have a name collision. The second function is to ensure that the
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chosen names are meaningful to all of the design team. It is quite
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chosen names are meaningful to all of the design team. It is quite
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common for designers to select names
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common for designers to select names
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that only make sense to themselves and no one else on the team. The
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that only make sense to themselves and no one else on the team. The
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third function
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third function
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is to ensure that all rtl code follows a consistent format so that it
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is to ensure that all rtl code follows a consistent format so that it
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may be parsed
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may be parsed
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by various eda tools.
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by various eda tools.
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</p>
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</p>
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<h3 class="western"><br>
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<h3 class="western"><br>
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</h3>
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</h3>
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<h3 class="western"><br>
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<h3 class="western"><br>
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</h3>
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</h3>
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<h3 class="western"><br>
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<h3 class="western"><br>
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</h3>
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</h3>
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<h3 class="western">Signal ,Port and Pad Names<br>
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<h3 class="western">Signal ,Port and Pad Names<br>
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</h3>
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</h3>
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<p>Signals define the nodes inside of a component and each node
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<p>Signals define the nodes inside of a component and each node
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must have a unique name. That signal name becomes the port name when a
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must have a unique name. That signal name becomes the port name when a
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node is ported up the hierarchy. The port names become the pad names at
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node is ported up the hierarchy. The port names become the pad names at
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the top level. All of these exist in the same name space along
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the top level. All of these exist in the same name space along
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with other items such as instance names. Managing this name space is
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with other items such as instance names. Managing this name space is
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crucial.<br>
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crucial.<br>
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</p>
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</p>
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<p><br>
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<p><br>
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There are two distinct groups that use these names. The IC design team
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There are two distinct groups that use these names. The IC design team
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is one group and it will use all three. The other group consists
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is one group and it will use all three. The other group consists
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of System designers,PCB designers, Board Test engineers etc.<br>
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of System designers,PCB designers, Board Test engineers etc.<br>
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They only access the chip via the pad names and never see the internal
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They only access the chip via the pad names and never see the internal
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ones. These two groups have incompatible objectives. The IC
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ones. These two groups often have incompatible objectives. The IC
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design team is dealing with millions of names and needs a naming scheme
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design team is dealing with millions of names and needs a naming scheme
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that produces long descriptive names that won't collide and conveys
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that produces long descriptive names that won't collide and conveys
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information about the signals function. <br>
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information about the signals function. <br>
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</p>
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</p>
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<p>The rest of the world is only dealing with a few hundred or thousand
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<p>The rest of the world is only dealing with a few hundred or thousand
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names. They also have their own naming requirements. These typically
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names. They also have their own naming requirements as well. These
|
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typically
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are:<br>
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are:<br>
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</p>
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</p>
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<p><br>
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<p><br>
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</p>
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</p>
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<ul>
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<ul>
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<li>Short Names that fit on a schematic graphic symbol. If you
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<li>Short Names that fit on a schematic graphic symbol. If you
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have 99 short names and 1 long one then you have a long column and
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have 99 short names and 1 long one then you have a long column and
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wasted white space on your schematic.</li>
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wasted white space on your schematic.</li>
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</ul>
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</ul>
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<br>
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<br>
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<ul>
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<ul>
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<li>Capital Letters. They make a packed schematic
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<li>Capital Letters. They make a packed schematic
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readable. You don't want your board designers trying to guess if it's a
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readable. You don't want your board designers squinting at a sheet
|
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trying to guess if it's a
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1 or a l.</li>
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1 or a l.</li>
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</ul>
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</ul>
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<br>
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<br>
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<ul>
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<ul>
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<li>ATE naming requirements. Do you know what the IEEE 1149.1
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<li>ATE naming requirements. Do you know what the IEEE 1149.1
|
pad naming rules are? If not then you shouldn't be selecting pad names.</li>
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pad naming rules are? If not then you better not try to pick any pad
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names.</li>
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</ul>
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</ul>
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<br>
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<br>
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<br>
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<br>
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The guideline for selecting pad names is that the IC design team should
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The guideline for selecting pad names is that the IC design team should
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not attempt to pick pad names based on the internal signal names.
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not attempt to pick pad names based on the internal signal names.
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They should first meet all of the PCA customers requirements without
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They should first meet all of the PCA customers requirements without
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regard to what names are chosen for the internal signals. Name
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regard to what names are chosen for the internal signals. Name
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collisions are avoided by ensuring that ALL pad names start with a
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collisions are avoided by ensuring that ALL pad names start with a
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capital letter and that all internal names start with a small
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capital letter and that all internal names start with a small
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one. <br>
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one. <br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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For internal signal and port names you must first find the four pieces
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For internal signal and port names you must first find the four pieces
|
of information that will uniquely identify every signal in the design.
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of information that will uniquely identify every signal in the design.
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These are:<br>
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These are:<br>
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<br>
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<br>
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<br>
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<br>
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<ul>
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<ul>
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<li>Interface Name You don't want 5 different ways
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<li>Interface Name You don't want 5 different ways
|
to spell clock in a design. Each team must agree
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to spell clock in a design. Each team must agree
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on common signal names and everyone must follow the rules. These
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on common signal names and everyone must follow the rules. These
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are called standard interfaces. The team must create a document that
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are called standard interfaces. The team must create a document that
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lists all the standard interfaces and their names. It is
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lists all the standard interfaces and their names. It is
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ESSENTIAL that once a standard is chosen then all signals covered by
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ESSENTIAL that once a standard is chosen then all signals covered by
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that standards MUST follow the naming rules and the no signals that are
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that standards MUST follow the naming rules and the no signals that are
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not covered by the standard are allowed to use its name.<br>
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not covered by the standard are allowed to use its name.<br>
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</li>
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</li>
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</ul>
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</ul>
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<br>
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<br>
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<ul>
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<ul>
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<li>Sub_member If the standard
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<li>Sub_member If the standard
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interface has more than one signal then you must also define the
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interface has more than one signal then you must also define the
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names for each sub_member as part of the standard <br>
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names for each sub_member as part of the standard <br>
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</li>
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</li>
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</ul>
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</ul>
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<br>
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<br>
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<br>
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<br>
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<ul>
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<ul>
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<li>ad
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<li>Ad
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hoc
|
hoc
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If a signal is not defined by a standard interface then an ad hoc
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If
|
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a signal is not defined by a standard interface then an ad hoc
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signal can be created based on the designers insight. If a module has 2
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signal can be created based on the designers insight. If a module has 2
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or more signals with the same standard interface then a ad hoc field is
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or more signals with the same standard interface then a ad hoc field is
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needed to distinguish between them.</li>
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needed to distinguish between them.</li>
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</ul>
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</ul>
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<br>
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<br>
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<ul>
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<ul>
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<li>Driving Instance This is the instance name that
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<li>Driving Instance This is the instance name that
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is driving the signal. Wired or tristate logic is not allowed. There
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is driving the signal. Wired or tristate logic is not allowed. There
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will be one and only one driver per node.</li>
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will be one and only one driver per node.</li>
|
</ul>
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</ul>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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You can create signal names by simply gathering this information and
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You can create signal names by simply gathering akk this information
|
concatenating it into a name but it is perfectly acceptable to
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and
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drop any field(s) if they are not needed to uniquely identify a node.<br>
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concatenating it into a valid signal name. While you can use all
|
For example a IC design may have a signal named "clk". Clk is the
|
four fields,it is acceptable to
|
|
drop any field(s) if they are not needed to <br>
|
|
uniquely identify a node. For example a IC design may have a signal
|
|
named "clk". Clk is the
|
standard interface name for a clock signal so we know that it is a
|
standard interface name for a clock signal so we know that it is a
|
clock. The clock interface has two sub_members - rising edge and
|
clock. The clock interface has two sub_members - rising edge and
|
falling edge. If you have N sub_members then you only have to
|
falling edge. If you have N sub_members then you only have to
|
identify N-1 of them. In this case the standard chooses _n for falling
|
identify N-1 of them. In this case the standard chooses _n for falling
|
edge clocks and nothing for rising edge. clk is a rising edge clock. An
|
edge clocks and nothing for rising edge. clk is a rising edge clock. An
|
ad hoc field is needed if the design has more than one clock and we
|
ad hoc field is needed if the design has more than one clock and we
|
have several - 2x, 4x 1.5 x etc. But again we only have to add this to
|
have several - 2x, 4x 1.5 x etc. But again we only have to add this to
|
all but one of the clocks. clk is a 1x clock. This design only has one
|
all but one of the clocks. clk is a 1x clock. This design only has one
|
clock generator so we don't need to add the driving instance. If
|
clock generator so we don't need to add the driving instance. If
|
a second clock generator is added then all of those clocks must include
|
a second clock generator is added then all of those clocks must include
|
the driving instance in their name.<br>
|
the driving instance in their name.<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
Besides defining all of the standard interfaces the design team must
|
Besides defining all of the standard interfaces the design team must
|
also define a field separator such as _ (underscore) as the way to
|
also define a field separator such as _ (underscore) as the way to
|
separate the different fields that are combined to make a signal or
|
separate the different fields that are combined to make a signal or
|
port name. But the most important decision of all is the order
|
port name. But the most important decision of all is the order
|
that the fields are assembled to make up a name. This is like the Big
|
that the fields are assembled to make up a name. This is like the Big
|
Endian/Little Endian issue. They both have their strengths and
|
Endian/Little Endian issue. They both have their strengths and
|
weaknesses and it really doesn't matter which one you pick. BUT it is
|
weaknesses and it really doesn't matter which one you pick. BUT it is
|
essential that the design team picks one and everybody does it that
|
essential that the design team picks one and everybody does it that
|
way. <br>
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way. <br>
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<br>
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<br>
|
Signal and port names are even worse because with four fields you can
|
Signal and port names are even worse because with four fields you can
|
have 24 possible signal names for each node. Unless everyone on
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have 24 possible signal names for each node. Unless everyone on
|
the design team adheres to one order then it will be chaos when you try
|
the design team adheres to one order then it will be chaos when you try
|
to architect and synthesize a design.<br>
|
to architect and synthesize a design.<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
The recommended order for fields in a signal/port name is<br>
|
The recommended order for fields in a signal/port name is<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
Driving_instance_(sep)_Ad
|
Driving_instance_(sep)_Ad
|
hoc_(sep)_Interface_(sep)_Sub_member<br>
|
hoc_(sep)_Interface_(sep)_Sub_member<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
This ordering gives us the ability to have our signal names follow
|
This ordering gives us the ability to have our signal names follow
|
their function as the signals pass up and down the hierarchy. It also
|
their function as the signals pass up and down the hierarchy. It also
|
gives us an easy rule to follow when we need to pick a signal name. All
|
gives us an easy rule to follow when we need to pick a signal name. All
|
that you need to do is find the instance name of the module that is
|
that you need to do is find the instance name of the module that is
|
driving that signal and combine it with the port name from that
|
driving that signal and combine it with the port name from that
|
module. Since instance names are unique inside a design and port
|
module. Since instance names are unique inside a design and port
|
names are unique inside of a module then this rule guarantees that no
|
names are unique inside of a module then this rule guarantees that no
|
other signal will use that name.<br>
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other signal will use that name.<br>
|
<br>
|
<br>
|
By following this rule a signal name will grow as it progresses up the
|
By following this rule a signal name will grow as it progresses up the
|
hierarchy. At each new level a new instance name is
|
hierarchy. At each new level a new instance name is
|
stuck on the front end and the instance name
|
stuck on the front end and the instance name
|
from the lower level becomes part of the ad hoc field. Each
|
from the lower level becomes part of the ad hoc field. Each
|
name contains a history of how it was created and what it does.<br>
|
name contains a history of how it was created and what it does.<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
There are some special cases that can occur and these rules should be
|
There are some special cases that can occur and these rules should be
|
followed:<br>
|
followed:<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<ul>
|
<ul>
|
<li>There is one sub_member that can be used on a ad hoc signal
|
<li>There is one sub_member that can be used on a ad hoc signal
|
that is not defined as a standard interface. That sub_member is active
|
that is not defined as a standard interface. That sub_member is active
|
low (_n).</li>
|
low (_n).</li>
|
</ul>
|
</ul>
|
<br>
|
<br>
|
<ul>
|
<ul>
|
<li>If a standard interface includes a signal that is itself defined
|
<li>If a standard interface includes a signal that is itself defined
|
as another standard interface then the interface name of the
|
as another standard interface then the interface name of the
|
child becomes the sub member name for the parent. This usually occurs
|
child becomes the sub member name for the parent. This usually occurs
|
when a clock or reset is included in a bus interface. This ensures that
|
when a clock or reset is included in a bus interface. This ensures that
|
when parsing the signal name it will match on both interfaces. If there
|
when parsing the signal name it will match on both interfaces. If there
|
are multiples of this interface then a ad hoc field must be perpended
|
are multiples of this interface then a ad hoc field must be perpended
|
to the sub_member interface.</li>
|
to the sub_member interface.</li>
|
</ul>
|
</ul>
|
<br>
|
<br>
|
<ul>
|
<ul>
|
<li>If the driving instance is not known such as a module where the
|
<li>If the driving instance is not known such as a module where the
|
signal is an input port then the instance and port of a receiving
|
signal is an input port then the instance and port of a receiving
|
instance may be used instead.</li>
|
instance may be used instead.</li>
|
</ul>
|
</ul>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
Again remember that any field may be dropped if it is not needed to
|
Again remember that any field may be dropped if it is not needed to
|
uniquely identify the node<br>
|
uniquely identify the node<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<img style="width: 800px; height: 600px;" alt=""
|
<img style="width: 800px; height: 600px;" alt=""
|
src="../png/naming_guide_1.png"><br>
|
src="../png/naming_guide_1.png"><br>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
<br>
|
<br>
|
Here is an example of how this works in a real design. A router IC has
|
Here is an example of how this works in a real design. A router IC has
|
24 instances of a ethernet interface. Each instance controls a transmit
|
24 instances of a ethernet interface. Each instance controls a transmit
|
sram buffer and a receive sram buffer. There are four instances in a
|
sram buffer and a receive sram buffer. There are four instances in a
|
bank and the bank is instantiated six times. The receive write
|
bank and the bank is instantiated six times. The receive write
|
data for the third interface in the second bank
|
data for the third interface in the second bank
|
originates in a register bank deep inside a submodule. The name
|
originates in a register bank deep inside a submodule. The name
|
of this register is sram_wdata and that was chosen because the sram bus
|
of this register is sram_wdata and that was chosen because the sram bus
|
is a standard interface and wdata is the sub_member for the wdata. As
|
is a standard interface and wdata is the sub_member for the wdata. As
|
it passes through the hierarchy the driving instance name is prepended
|
it passes through the hierarchy the driving instance name is prepended
|
on the front. It always parses as a sram wdata signal but the ad hoc
|
on the front. It always parses as a sram wdata signal but the ad hoc
|
field keeps growing.</p>
|
field keeps growing.</p>
|
<p><br>
|
<p><br>
|
If the clock signal is also included in the sram interface then it's
|
If the clock signal is also included in the sram interface then it's
|
name would be:</p>
|
name would be:</p>
|
<p> <br>
|
<p> <br>
|
</p>
|
</p>
|
<p>
|
<p>
|
bank_2_eth_3_sram_clk<br>
|
bank_2_eth_3_sram_clk<br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p>It would parse as both a clock signal and a sram signal. If this
|
<p>It would parse as both a clock signal and a sram signal. If this
|
were a dual port sram then the signal would be:</p>
|
were a dual port sram then the signal would be:</p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p>
|
<p>
|
bank_2_eth_3_sram_a_clk <br>
|
bank_2_eth_3_sram_a_clk
|
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p>Notice that there is an ad hoc field both before and after the sram
|
<p>Notice that there is an ad hoc field both before and after the sram
|
interface name and it still parses as both a clock and a sram signal.<br>
|
interface name and it still parses as both a clock and a sram signal.<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p>If you want to synthesize the bank of 4 controllers then you will
|
<p>If you want to synthesize the bank of 4 controllers then you will
|
need to set an output delay on the sram outputs as a placeholder for
|
need to set an output delay on the sram outputs as a placeholder for
|
the setup and routing delays in the full chip. To do this you need the
|
the setup and routing delays in the full chip. To do this you need the
|
full instance name of the source registers as seen from the top level.
|
full instance name of the source registers as seen from the top level.
|
Assuming you use the standard _reg convention it would be:<br>
|
Assuming you use the standard _reg convention it would be:<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
|
|
eth_3/rx/sram_wdata_reg<br>
|
eth_3/rx/sram_wdata_reg<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<br>
|
<br>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<h2>Standard Interfaces<br>
|
<h2>Standard Interfaces<br>
|
</h2>
|
</h2>
|
<p></p>
|
<p></p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
|
<h3 class="western">Clock <br>
|
|
</h3>
|
<h3 class="western">Clock <br></h3>
|
|
<p><br>
|
<p><br>
|
A clock is a signal that drives the clock port of a flipflop.<br>
|
A clock is a signal that drives the clock port of a flipflop.<br>
|
</p>
|
</p>
|
<br>
|
<br>
|
<table style="text-align: left; width: 500px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
|
<table style="text-align: left; width: 500px; height: 120px;" border="8"
|
|
cellpadding="4" cellspacing="4">
|
<tbody>
|
<tbody>
|
<tr>
|
<tr>
|
<td style="vertical-align: top;">Interface<br> </td>
|
<td style="vertical-align: top;">Interface<br>
|
<td style="vertical-align: top;">Clock<br> </td>
|
</td>
|
<td style="vertical-align: top;">Name<br> </td>
|
<td style="vertical-align: top;">Clock<br>
|
<td style="vertical-align: top;">Sub <br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">Name<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;">Sub <br>
|
<td style="vertical-align: top;"> <br> </td>
|
</td>
|
<td style="vertical-align: top;">CLK<br> </td>
|
</tr>
|
<td style="vertical-align: top;"> <br> </td>
|
<tr>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">Rising Edge<br> </td>
|
</td>
|
<td style="vertical-align: top;">CLK<br> </td>
|
<td style="vertical-align: top;">CLK<br>
|
<td style="vertical-align: top;"> <br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
</tr>
|
<td style="vertical-align: top;">Falling Edge<br> </td>
|
<tr>
|
<td style="vertical-align: top;">CLK<br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">_N<br> </td>
|
</td>
|
|
<td style="vertical-align: top;">Rising Edge<br>
|
|
</td>
|
|
<td style="vertical-align: top;">CLK<br>
|
|
</td>
|
|
<td style="vertical-align: top;"> <br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Falling Edge<br>
|
|
</td>
|
|
<td style="vertical-align: top;">CLK<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_N<br>
|
|
</td>
|
</tr>
|
</tr>
|
</tbody>
|
</tbody>
|
</table>
|
</table>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
|
<h3 class="western">Reset <br>
|
|
</h3>
|
|
|
<h3 class="western">Reset <br></h3>
|
|
<p><br>
|
<p><br>
|
A reset is a signal forces nodes into a known safe state<br>
|
A reset is a signal forces nodes into a known safe state<br>
|
</p>
|
</p>
|
<br>
|
<br>
|
<table style="text-align: left; width: 500px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
|
<table style="text-align: left; width: 500px; height: 120px;" border="8"
|
|
cellpadding="4" cellspacing="4">
|
<tbody>
|
<tbody>
|
<tr>
|
<tr>
|
<td style="vertical-align: top;">Interface<br> </td>
|
<td style="vertical-align: top;">Interface<br>
|
<td style="vertical-align: top;">Reset<br> </td>
|
</td>
|
<td style="vertical-align: top;">Name<br> </td>
|
<td style="vertical-align: top;">Reset<br>
|
<td style="vertical-align: top;">Sub <br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">Name<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;">Sub <br>
|
<td style="vertical-align: top;"> <br> </td>
|
</td>
|
<td style="vertical-align: top;">RESET<br> </td>
|
</tr>
|
<td style="vertical-align: top;"> <br> </td>
|
<tr>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">Active high sync<br> </td>
|
</td>
|
<td style="vertical-align: top;">RESET<br> </td>
|
<td style="vertical-align: top;">RESET<br>
|
<td style="vertical-align: top;"> <br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
</tr>
|
<td style="vertical-align: top;">Active Low async<br> </td>
|
<tr>
|
<td style="vertical-align: top;">RESET<br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">_N<br> </td>
|
</td>
|
|
<td style="vertical-align: top;">Active high sync<br>
|
|
</td>
|
|
<td style="vertical-align: top;">RESET<br>
|
|
</td>
|
|
<td style="vertical-align: top;"> <br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Active Low async<br>
|
|
</td>
|
|
<td style="vertical-align: top;">RESET<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_N<br>
|
|
</td>
|
</tr>
|
</tr>
|
</tbody>
|
</tbody>
|
</table>
|
</table>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
|
<h3 class="western">Pads <br>
|
|
</h3>
|
|
|
|
|
|
|
<h3 class="western">Pads <br></h3>
|
|
<p><br>
|
<p><br>
|
Pads are the connections made between the pad_ring and the core.<br>
|
Pads are the connections made between the pad_ring and the core.<br>
|
</p>
|
</p>
|
<br>
|
<br>
|
<table style="text-align: left; width: 500px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
|
<table style="text-align: left; width: 500px; height: 120px;" border="8"
|
|
cellpadding="4" cellspacing="4">
|
<tbody>
|
<tbody>
|
<tr>
|
<tr>
|
<td style="vertical-align: top;">Interface<br> </td>
|
<td style="vertical-align: top;">Interface<br>
|
<td style="vertical-align: top;">Pads<br> </td>
|
</td>
|
<td style="vertical-align: top;">Name<br> </td>
|
<td style="vertical-align: top;">Pads<br>
|
<td style="vertical-align: top;">Sub <br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">Name<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;">Sub <br>
|
<td style="vertical-align: top;"> <br> </td>
|
</td>
|
<td style="vertical-align: top;">PAD<br> </td>
|
</tr>
|
<td style="vertical-align: top;"> <br> </td>
|
<tr>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">output<br> </td>
|
</td>
|
<td style="vertical-align: top;">PAD<br> </td>
|
<td style="vertical-align: top;">PAD<br>
|
<td style="vertical-align: top;">_OUT <br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
</tr>
|
<td style="vertical-align: top;">Input<br> </td>
|
<tr>
|
<td style="vertical-align: top;">PAD<br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">_IN<br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">output<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;">PAD<br>
|
<td style="vertical-align: top;">Enable<br> </td>
|
</td>
|
<td style="vertical-align: top;">PAD<br> </td>
|
<td style="vertical-align: top;">_OUT <br>
|
<td style="vertical-align: top;">_OE<br> </td>
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Input<br>
|
|
</td>
|
|
<td style="vertical-align: top;">PAD<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_IN<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Enable<br>
|
|
</td>
|
|
<td style="vertical-align: top;">PAD<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_OE<br>
|
|
</td>
|
</tr>
|
</tr>
|
</tbody>
|
</tbody>
|
</table>
|
</table>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
|
<h3 class="western">Sram <br>
|
|
</h3>
|
|
|
<h3 class="western">Sram <br></h3>
|
|
<p><br>
|
<p><br>
|
Sram signals connect between the core and an instantiated memory cell.<br>
|
Sram signals connect between the core and an instantiated memory cell.<br>
|
</p>
|
</p>
|
<br>
|
<br>
|
<table style="text-align: left; width: 500px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
|
<table style="text-align: left; width: 500px; height: 120px;" border="8"
|
|
cellpadding="4" cellspacing="4">
|
<tbody>
|
<tbody>
|
<tr>
|
<tr>
|
<td style="vertical-align: top;">Interface<br> </td>
|
<td style="vertical-align: top;">Interface<br>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
</td>
|
<td style="vertical-align: top;">Name<br> </td>
|
<td style="vertical-align: top;">SRAM<br>
|
<td style="vertical-align: top;">Sub <br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">Name<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;">Sub <br>
|
<td style="vertical-align: top;"> <br> </td>
|
</td>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
</tr>
|
<td style="vertical-align: top;"> <br> </td>
|
<tr>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">RW Address<br> </td>
|
</td>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
<td style="vertical-align: top;">SRAM<br>
|
<td style="vertical-align: top;">_ADDR <br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
</tr>
|
<td style="vertical-align: top;">Read Address<br> </td>
|
<tr>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">_RADDR <br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">RW Address<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;">SRAM<br>
|
<td style="vertical-align: top;">Write Address<br> </td>
|
</td>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
<td style="vertical-align: top;">_ADDR <br>
|
<td style="vertical-align: top;">_WADDR <br> </td>
|
</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">Write Data<br> </td>
|
</td>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
<td style="vertical-align: top;">Read Address<br>
|
<td style="vertical-align: top;">_WDATA<br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">SRAM<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;">_RADDR <br>
|
<td style="vertical-align: top;">Read Data<br> </td>
|
</td>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
</tr>
|
<td style="vertical-align: top;">_RDATA<br> </td>
|
<tr>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
|
</td>
|
|
<td style="vertical-align: top;">Write Address<br>
|
|
</td>
|
<tr>
|
<td style="vertical-align: top;">SRAM<br>
|
<td style="vertical-align: top;"><br> </td>
|
</td>
|
<td style="vertical-align: top;">Ram Select<br> </td>
|
<td style="vertical-align: top;">_WADDR <br>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
</td>
|
<td style="vertical-align: top;">_CS<br> </td>
|
</tr>
|
</tr>
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
<tr>
|
<td style="vertical-align: top;">Write Data<br>
|
<td style="vertical-align: top;"><br> </td>
|
</td>
|
<td style="vertical-align: top;">Write Enable<br> </td>
|
<td style="vertical-align: top;">SRAM<br>
|
<td style="vertical-align: top;">SRAM<br> </td>
|
</td>
|
<td style="vertical-align: top;">_WR<br> </td>
|
<td style="vertical-align: top;">_WDATA<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Read Data<br>
|
|
</td>
|
|
<td style="vertical-align: top;">SRAM<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_RDATA<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Ram Select<br>
|
|
</td>
|
|
<td style="vertical-align: top;">SRAM<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_CS<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Write Enable<br>
|
|
</td>
|
|
<td style="vertical-align: top;">SRAM<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_WR<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Read Enable<br>
|
|
</td>
|
|
<td style="vertical-align: top;">SRAM<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_RD<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Bit Write Enable<br>
|
|
</td>
|
|
<td style="vertical-align: top;">SRAM<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_BE<br>
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</td>
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</tr>
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<tr>
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<td style="vertical-align: top;"><br>
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</td>
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|
<td style="vertical-align: top;">Clock<br>
|
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</td>
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<td style="vertical-align: top;">SRAM<br>
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</td>
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<td style="vertical-align: top;">_CLK<br>
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|
</td>
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</tr>
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</tr>
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|
|
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<tr>
|
|
<td style="vertical-align: top;"><br> </td>
|
|
<td style="vertical-align: top;">Read Enable<br> </td>
|
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<td style="vertical-align: top;">SRAM<br> </td>
|
|
<td style="vertical-align: top;">_RD<br> </td>
|
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</tr>
|
|
|
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<tr>
|
|
<td style="vertical-align: top;"><br> </td>
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|
<td style="vertical-align: top;">Bit Write Enable<br> </td>
|
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<td style="vertical-align: top;">SRAM<br> </td>
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<td style="vertical-align: top;">_BE<br> </td>
|
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</tr>
|
|
|
|
<tr>
|
|
<td style="vertical-align: top;"><br> </td>
|
|
<td style="vertical-align: top;">Clock<br> </td>
|
|
<td style="vertical-align: top;">SRAM<br> </td>
|
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<td style="vertical-align: top;">_CLK<br> </td>
|
|
</tr>
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|
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|
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</tbody>
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</tbody>
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</table>
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</table>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
|
<h3 class="western">Wishbone Bus <br>
|
<h3 class="western">Wishbone Bus <br></h3>
|
</h3>
|
<p><br>
|
<p><br>
|
The wishbone bus provides microprocessor interconnection .<br>
|
The wishbone bus provides microprocessor interconnection .<br>
|
</p>
|
</p>
|
<br>
|
<br>
|
<table style="text-align: left; width: 500px; height: 120px;" border="8" cellpadding="4" cellspacing="4">
|
<table style="text-align: left; width: 500px; height: 120px;" border="8"
|
|
cellpadding="4" cellspacing="4">
|
<tbody>
|
<tbody>
|
<tr>
|
<tr>
|
<td style="vertical-align: top;">Interface<br> </td>
|
<td style="vertical-align: top;">Interface<br>
|
<td style="vertical-align: top;">Wishbone<br> </td>
|
</td>
|
<td style="vertical-align: top;">Name<br> </td>
|
<td style="vertical-align: top;">Wishbone<br>
|
<td style="vertical-align: top;">Sub <br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">Name<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;">Sub <br>
|
<td style="vertical-align: top;">Address<br> </td>
|
</td>
|
<td style="vertical-align: top;">WB<br> </td>
|
</tr>
|
<td style="vertical-align: top;">_ADR<br> </td>
|
<tr>
|
</tr>
|
<td style="vertical-align: top;"> <br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"> <br> </td>
|
<td style="vertical-align: top;">Address<br>
|
<td style="vertical-align: top;">Write Data<br> </td>
|
</td>
|
<td style="vertical-align: top;">WB<br> </td>
|
<td style="vertical-align: top;">WB<br>
|
<td style="vertical-align: top;"> _WDAT<br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">_ADR<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
</tr>
|
<td style="vertical-align: top;">Read Data<br> </td>
|
<tr>
|
<td style="vertical-align: top;">WB<br> </td>
|
<td style="vertical-align: top;"> <br>
|
<td style="vertical-align: top;">_RDAT<br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">Write Data<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;">WB<br>
|
<td style="vertical-align: top;">Write Enable<br> </td>
|
</td>
|
<td style="vertical-align: top;">WB<br> </td>
|
<td style="vertical-align: top;"> _WDAT<br>
|
<td style="vertical-align: top;">_WE<br> </td>
|
</td>
|
</tr>
|
</tr>
|
<tr>
|
<tr>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;"><br>
|
<td style="vertical-align: top;">Byte Select<br> </td>
|
</td>
|
<td style="vertical-align: top;">WB<br> </td>
|
<td style="vertical-align: top;">Read Data<br>
|
<td style="vertical-align: top;">_SEL<br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">WB<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;">_RDAT<br>
|
<td style="vertical-align: top;">Cycle<br> </td>
|
</td>
|
<td style="vertical-align: top;">WB<br> </td>
|
</tr>
|
<td style="vertical-align: top;">_CYC<br> </td>
|
<tr>
|
</tr>
|
<td style="vertical-align: top;"><br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;">Write Enable<br>
|
<td style="vertical-align: top;">Data Strobe<br> </td>
|
</td>
|
<td style="vertical-align: top;">WB<br> </td>
|
<td style="vertical-align: top;">WB<br>
|
<td style="vertical-align: top;">_STB<br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">_WE<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
</tr>
|
<td style="vertical-align: top;">Acknowledge<br> </td>
|
<tr>
|
<td style="vertical-align: top;">WB<br> </td>
|
<td style="vertical-align: top;"><br>
|
<td style="vertical-align: top;">_ACK<br> </td>
|
</td>
|
</tr>
|
<td style="vertical-align: top;">Byte Select<br>
|
<tr>
|
</td>
|
<td style="vertical-align: top;"><br> </td>
|
<td style="vertical-align: top;">WB<br>
|
<td style="vertical-align: top;">CTI<br> </td>
|
</td>
|
<td style="vertical-align: top;">WB<br> </td>
|
<td style="vertical-align: top;">_SEL<br>
|
<td style="vertical-align: top;">_CTI<br> </td>
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Cycle<br>
|
|
</td>
|
|
<td style="vertical-align: top;">WB<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_CYC<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Data Strobe<br>
|
|
</td>
|
|
<td style="vertical-align: top;">WB<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_STB<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">Acknowledge<br>
|
|
</td>
|
|
<td style="vertical-align: top;">WB<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_ACK<br>
|
|
</td>
|
|
</tr>
|
|
<tr>
|
|
<td style="vertical-align: top;"><br>
|
|
</td>
|
|
<td style="vertical-align: top;">CTI<br>
|
|
</td>
|
|
<td style="vertical-align: top;">WB<br>
|
|
</td>
|
|
<td style="vertical-align: top;">_CTI<br>
|
|
</td>
|
</tr>
|
</tr>
|
</tbody>
|
</tbody>
|
</table>
|
</table>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
<p></p>
|
<p></p>
|
<br>
|
<br>
|
<br>
|
<br>
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
</body>
|
</body>
|
</html>
|
</html>
|
|
|
