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<p><br>
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<p><br>
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<h1><a name="socgen_project"></a>Design considerations for Reset
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<h1><a name="socgen_project"></a>Design considerations for Reset
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Systems<br>
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Systems<br>
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</h1>
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</h1>
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<p><br>
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<p><br>
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<br>
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<br>
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</p>
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</p>
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<p>In a world as fast moving as the semiconductor industry it is
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<p>In a world as fast moving as the semiconductor industry it is
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essential that all designers continuously update their knowledge as the
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essential that all designers continuously update their knowledge as the
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technology changes. It is very easy to become complacent and then
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technology changes. It is very easy to become complacent and then
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suddenly discover that the techniques that have served you for many
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suddenly discover that the techniques that have served you for many
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years no longer work. <br>
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years no longer work. <br>
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<br>
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<br>
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</p>
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</p>
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<p>This paper was written to explore some of the mistakes that reset
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<p>This paper was written to explore some of the mistakes that reset
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system designers have made over the years and why they are no longer
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system designers have made over the years and why they are no longer
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true.<br>
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true.<br>
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</p>
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</p>
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<h3 class="western"><br>
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<h3 class="western"><br>
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</h3>
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</h3>
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<h3 class="western"></h3>
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<h3 class="western"></h3>
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<h3 class="western">Do we really need a reset system? <br>
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<h3 class="western">Do we really need a reset system? <br>
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</h3>
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</h3>
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<p>Actually you don't. It is a good design practice to ensure that
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<p>Actually you don't. It is a good design practice to ensure that
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there are no dead end states in your logic and that any state will
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there are no dead end states in your logic and that any state will
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eventually lead into a valid operating mode. For many years designs
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eventually lead into a valid operating mode. For many years designs
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were simple and robust enough that they would function even if they
|
were simple and robust enough that they would function even if they
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were enabled without a reset. Then along came embedded processors and
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were enabled without a reset. Then along came embedded processors and
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the world became much more complex. I have seen some pretty audacious
|
the world became much more complex. I have seen some pretty audacious
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attempts to create a watchdog to detect and restart a lost system
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attempts to create a watchdog to detect and restart a lost system
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but the best that they can do is to improve the odds that the system
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but the best that they can do is to improve the odds that the system
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will recover. None of them were 100%.<br>
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will recover. None of them were 100%.<br>
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</p>
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</p>
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<p>It is possible that you do not need to reset all the storage
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<p>It is possible that you do not need to reset all the storage
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elements in a design. In many cases the data is reloaded shortly before
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elements in a design. In many cases the data is reloaded shortly before
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it is needed and it doesn't care what it was before that time. Some
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it is needed and it doesn't care what it was before that time. Some
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designers will leave certain storage elements off of the power on reset
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designers will leave certain storage elements off of the power on reset
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because it has no effect on the operation.<br>
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because it has no effect on the operation.<br>
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</p>
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</p>
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<p>BUT.<br>
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<p>BUT.<br>
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</p>
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</p>
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<p>There was a mathematician named Fermat who came up with a theorem
|
<p>There was a mathematician named Fermat who came up with a theorem
|
that eventually became known as Fermat's last theorem. It was a simple
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that eventually became known as Fermat's last theorem. It was a simple
|
little equation that worked in every test case that they threw at
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little equation that worked in every test case that they threw at
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it and they threw a lot of test cases at it. But it took over 350 years
|
it and they threw a lot of test cases at it. But it took over 350 years
|
before someone could prove that it would really work in all cases.</p>
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before someone could prove that it would really work in all cases.</p>
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<p><br>
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<p><br>
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If you allow your designers the option to leave storage elements off
|
If you allow your designers the option to leave storage elements off
|
the power on reset system then they will come up with these wonderful
|
the power on reset system then they will come up with these wonderful
|
little designs that appear to work and they will work in any test case
|
little designs that appear to work and they will work in any test case
|
that you throw at it. But it will take you FOREVER to fully verify that
|
that you throw at it. But it will take you FOREVER to fully verify that
|
it will work in all cases.<br>
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it will work in all cases.<br>
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</p>
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</p>
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<p>You do not need a power on reset system for your logic to work. You
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<p>You do not need a power on reset system for your logic to work. You
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need it in order to verify that your logic works. It takes
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need it in order to verify that your logic works. It takes
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longer to verify a design than it does to create it and not providing a
|
longer to verify a design than it does to create it and not providing a
|
100% known startup condition will make the verification effort that
|
100% known start up condition will make the verification effort that
|
much harder. All storage elements must be on a reset if only for test
|
much harder. All storage elements must be on a reset if only for test
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and verification purposes. If you have logic that must function during
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and verification purposes. If you have logic that must function during
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a power up reset then put it on a special reset that is only active in
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a power up reset then put it on a special reset that is only active in
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test mode.<br>
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test mode.<br>
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</p>
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</p>
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<br>
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<br>
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<h3 class="western">All components must come out of reset on exactly
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<h3 class="western">All components must come out of reset on exactly
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the same clock<br>
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the same clock<br>
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</h3>
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</h3>
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Thats true, or at least it was back in the 60's. Back then every
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That's true, or at least it was back in the 60's. Back then every
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component would come out of reset and start "componenting". The reset
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component would come out of reset and start "componenting". The reset
|
system acted like a conductor so that everybody started on the
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system acted like a conductor so that everybody started on the
|
same beat. Those types of systems are rare today. Most major chips have
|
same beat. Those types of systems are rare today. Most major chips have
|
one or more microprocessors in side so components come out of reset
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one or more microprocessors in side so components come out of reset
|
only to sit there waiting for the cpu to configure them and get them
|
only to sit there waiting for the cpu to configure them and get them
|
started. It doesn't matter what cycle you come out of reset on as
|
started. It doesn't matter what cycle you come out of reset on as
|
long as you are up and ready before someone else asks you to do
|
long as you are up and ready before someone else asks you to do
|
something. <br>
|
something. <br>
|
<br>
|
<br>
|
This has led to two prong approach to reset system design. The
|
This has led to two prong approach to reset system design. The
|
majority of the chip is on a large slow reset distribution
|
majority of the chip is on a large slow reset distribution
|
tree that doesn't even try to get everybody reset on
|
tree that doesn't even try to get everybody reset on
|
the same cycle. Then you have a second smaller and
|
the same cycle. Then you have a second smaller and
|
faster tree that only resets the cpu and anything else that can
|
faster tree that only resets the cpu and anything else that can
|
initiate activity. The fast reset is delayed long enough to
|
initiate activity. The fast reset is delayed long enough to
|
ensure that the slow reset is finished before starting the cpu. In
|
ensure that the slow reset is finished before starting the cpu. In
|
modern designs this can be a significant number of clock cycles. I have
|
modern designs this can be a significant number of clock cycles. I have
|
seen repairable memories where you had to hold off starting the cpu for
|
seen repairable memories where you had to hold off starting the cpu for
|
3000 clocks to ensure that any repair would be finished before the cpu
|
3000 clocks to ensure that any repair would be finished before the cpu
|
started.<br>
|
started.<br>
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<br>
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<br>
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<br>
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<br>
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<h3 class="western">You must design an asynchronous reset system<br>
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<h3 class="western">You must design an asynchronous reset system<br>
|
</h3>
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</h3>
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Absolutely. Most of the time your mission mode requirements will
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Absolutely. Most of the time your mission mode requirements will
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dictate that the power on reset system works even in the absence of
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dictate that the power on reset system works even in the absence of
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clock. If it doesn't then the test engineer will require that all pads
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clock. If it doesn't then the test engineer will require that all pads
|
must respond to an async reset in case a board is built missing it's
|
must respond to an async reset in case a board is built missing it's
|
clock. Asynchronous reset design is essential. A power up monitor
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clock. Asynchronous reset design is essential. A power up monitor
|
will drive the reset input active as the power is ramping
|
will drive the reset input active as the power is ramping
|
up. You will not have a clock at this time so the reset system must be
|
up. You will not have a clock at this time so the reset system must be
|
able to work without one.<br>
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able to work without one.<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
|
<h3 class="western">You must design your logic using synchronous design
|
<h3 class="western">You must design your logic using synchronous design
|
methods<br>
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methods<br>
|
</h3>
|
</h3>
|
Absolutely. Todays chips are huge. The only way that you can close
|
Absolutely. Today's chips are huge. The only way that you can close
|
timing on a large design is if everyone follows strict synchronous
|
timing on a large design is if everyone follows strict synchronous
|
design rules. The mistake that many of todays designers make is
|
design rules. The mistake that many of todays designers make is
|
that they think that because they have to design an asynchronous reset
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that they think that because they have to design an asynchronous reset
|
system that they get an exemption from following the rules for
|
system that they get an exemption from following the rules for
|
synchronous design. Sorry guys, it not one or the other its BOTH.
|
synchronous design. Sorry guys, it not one or the other its BOTH.
|
You have to design a asynchronous reset system but you cannot use any
|
You have to design a asynchronous reset system but you cannot use any
|
flip flops with an asynchronous reset port.<br>
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flip flops with an asynchronous reset port.<br>
|
<br>
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<br>
|
The funny thing is that synchronous design methodology is quite
|
The funny thing is that synchronous design methodology is quite
|
capable of creating an asynchronous reset system and
|
capable of creating an asynchronous reset system and
|
will actually give you a smaller and faster design that
|
will actually give you a smaller and faster design that
|
either of the traditional async only or sync only solutions.<br>
|
either of the traditional async only or sync only solutions.<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<h3 class="western">Don't worry about making the reset system
|
<h3 class="western">Don't worry about making the reset system
|
testable.The test engineer has a tool that will fix any problem in the
|
testable.The test engineer has a tool that will fix any problem in the
|
back end<br>
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back end<br>
|
</h3>
|
</h3>
|
That used to be true. The first thing a vendor does when they get a net
|
That used to be true. The first thing a vendor does when they get a net
|
list is to run a full drc that looks for dft issues. If anybody has any
|
list is to run a full drc that looks for dft issues. If anybody has any
|
signals crossing between the async reset port on a flipflop and
|
signals crossing between the async reset port on a flipflop and
|
either a D or a Q port then it flags it as a violation. So you can
|
either a D or a Q port then it flags it as a violation. So you can
|
either send it back to the customer and wait a week for them to find
|
either send it back to the customer and wait a week for them to find
|
it, fix it, and resynthesizes or you can eco in a test mux at the flop
|
it, fix it, and re-synthesizes or you can eco in a test mux at the flop
|
and have it fixed in 5 minutes. Everyone took the easy way out.<br>
|
and have it fixed in 5 minutes. Everyone took the easy way out.<br>
|
<br>
|
<br>
|
But then along came Logic equivalence checking (LEC). The final
|
But then along came Logic equivalence checking (LEC). The final
|
routed net list will be sent back and compared with the customers
|
routed net list will be sent back and compared with the customers
|
golden net list and all of these ecos will show up in the report.
|
golden net list and all of these ecos will show up in the report.
|
Now somebody has check out each and every item in the report
|
Now somebody has check out each and every item in the report
|
before you can release the masks. It now becomes easier for the
|
before you can release the masks. It now becomes easier for the
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customer to find and fix these errors before synthesis than it is to
|
customer to find and fix these errors before synthesis than it is to
|
deal with thousands of lec errors.<br>
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deal with thousands of lec errors.<br>
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<br>
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<br>
|
Besides with the newer processes the days when you could eco in a small
|
Besides with the newer processes the days when you could eco in a small
|
tweak on a routed net list and not have it break something are fast
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tweak on a routed net list and not have it break something are fast
|
disappearing. You will eco the rtl code and then re-synthesis and
|
disappearing. You will eco the rtl code and then re-synthesis and
|
reroute.<br>
|
reroute.<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<h3 class="western">You must use a sync_reset pragma if you design a
|
<h3 class="western">You must use a sync_reset pragma if you design a
|
synchronous reset system<br>
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synchronous reset system<br>
|
</h3>
|
</h3>
|
I cringe whenever I hear someone say this. If you do a
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I cringe whenever I hear someone say this. If you do a
|
synchronous reset design then you will find that your gate simulations
|
synchronous reset design then you will find that your gate simulations
|
will not run. Many of your flipflops will never reset to a known value.
|
will not run. Many of your flipflops will never reset to a known value.
|
They will get a valid clock and the reset in the block will be valid
|
They will get a valid clock and the reset in the block will be valid
|
but synthesis will have combined the reset logic in with the mission
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but synthesis will have combined the reset logic in with the mission
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mode logic and it will be distributed throughout the logic cone feeding
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mode logic and it will be distributed throughout the logic cone feeding
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the D input. It also uses the flops current state in order to compute
|
the D input. It also uses the flops current state in order to compute
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the next state. It creates a situation where if the flop has a 0
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the next state. It creates a situation where if the flop has a 0
|
or 1 in it then the logic will compute the next state as 0 when reset
|
or 1 in it then the logic will compute the next state as 0 when reset
|
is active. However if the flop is unknown as it is at power up then
|
is active. However if the flop is unknown as it is at power up then
|
verilog is unable to figure out the correct next state and it remains
|
verilog is unable to figure out the correct next state and it remains
|
at x.<br>
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at x.<br>
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<br>
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<br>
|
This is a simulation only issue as flops in real silicon will always
|
This is a simulation only issue as flops in real silicon will always
|
resolve to a valid state.<br>
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resolve to a valid state.<br>
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<br>
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<br>
|
Tool vendors created the sync_reset pragma so that you could tell the
|
Tool vendors created the sync_reset pragma so that you could tell the
|
tool not to combine the reset logic with the mission mode logic. You
|
tool not to combine the reset logic with the mission mode logic. You
|
place it at the very tip of the logic cone and it will remain there in
|
place it at the very tip of the logic cone and it will remain there in
|
gates.<br>
|
gates.<br>
|
<br>
|
<br>
|
So whats wrong with that?<br>
|
So whats wrong with that?<br>
|
<br>
|
<br>
|
The synthesis tool will make a list of all signals that enter the logic
|
The synthesis tool will make a list of all signals that enter the logic
|
cone along with the relative time it enters before the next clock
|
cone along with the relative time it enters before the next clock
|
edge. If it finds a early arriving signal entering the cone
|
edge. If it finds a early arriving signal entering the cone
|
closer to the tip than a late arriving one then it will try
|
closer to the tip than a late arriving one then it will try
|
to remap the logic and swap them so that the late
|
to remap the logic and swap them so that the late
|
arrival can move closer to tip. Ideally the
|
arrival can move closer to tip. Ideally the
|
latest signals are moved towards the tip and the early ones are moved
|
latest signals are moved towards the tip and the early ones are moved
|
to the rear. <br>
|
to the rear. <br>
|
<br>
|
<br>
|
The reset from a properly designed distribution tree and the feedback
|
The reset from a properly designed distribution tree and the feedback
|
signal from the flop that you are working on will always be two of the
|
signal from the flop that you are working on will always be two of the
|
earliest signals. They will get pushed up away from the tip of the cone
|
earliest signals. They will get pushed up away from the tip of the cone
|
simply to make room for the mission critical late signals. This is a
|
simply to make room for the mission critical late signals. This is a
|
good thing, you want this to happen. <br>
|
good thing, you want this to happen. <br>
|
<br>
|
<br>
|
The problem is that designers think that they must prove that the reset
|
The problem is that designers think that they must prove that the reset
|
system works in gate sims. Verilog is a great tool when every node is
|
system works in gate sims. Verilog is a great tool when every node is
|
in a known state but it is lousy when dealing with unknowns. There are
|
in a known state but it is lousy when dealing with unknowns. There are
|
times like this when it is possible to resolve a X into a known
|
times like this when it is possible to resolve a X into a known
|
value and it can't. There are also times when it will resolve an
|
value and it can't. There are also times when it will resolve an
|
X to a known value when it shouldn't. The only way to use verilog is to
|
X to a known value when it shouldn't. The only way to use verilog is to
|
start with everything in a known state and stop it when anything goes
|
start with everything in a known state and stop it when anything goes
|
X. That means theres a problem and nothing downstream from that X
|
X. That means there's a problem and nothing downstream from that
|
|
X
|
can be trusted.<br>
|
can be trusted.<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
You do not prove your reset system design in gates sims. You prove the
|
You do not prove your reset system design in gates sims. You prove the
|
design in rtl sims and use LEC to prove that gates matches the design
|
design in rtl sims and use LEC to prove that gates matches the design
|
that works. Then you use initial statements to force all flops to
|
that works. Then you use initial statements to force all flops to
|
a known state at startup and use gates sims to prove that everything
|
a known state at start up and use gates sims to prove that everything
|
else works. Verilog gates is the wrong tool to use to verify the reset
|
else works. Verilog gates is the wrong tool to use to verify the reset
|
system.<br>
|
system.<br>
|
<br>
|
<br>
|
You never use the sync_reset pragma unless you really like big slow
|
You never use the sync_reset pragma unless you really like big slow
|
designs.<br>
|
designs.<br>
|
<br>
|
<br>
|
<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
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<br>
|
<h3 class="western">Doing a synchronous reset design adds logic in the
|
<h3 class="western">Doing a synchronous reset design adds logic in the
|
D pathway and will slow down the design<br>
|
D pathway and will slow down the design<br>
|
</h3>
|
</h3>
|
<br>
|
<br>
|
Wrong. Adding logic in the critical path will slow down the design.
|
Wrong. Adding logic in the critical path will slow down the design.
|
Adding it into a non-critical path simply reduces slack in that path.
|
Adding it into a non-critical path simply reduces slack in that path.
|
If you put the reset logic at the very tip of the logic cone then you
|
If you put the reset logic at the very tip of the logic cone then you
|
are adding it into the critical path and the synthesis tool will move
|
are adding it into the critical path and the synthesis tool will move
|
it up the cone until it is in a safe location.<br>
|
it up the cone until it is in a safe location.<br>
|
<br>
|
<br>
|
Adding a synchronous reset system doesn't really add much logic to the
|
Adding a synchronous reset system doesn't really add much logic to the
|
design. The tools will first locate any mission mode logic that also
|
design. The tools will first locate any mission mode logic that also
|
forces the flop into the reset state and it will piggyback the reset
|
forces the flop into the reset state and it will piggyback the reset
|
system with that logic. You don't add gates , you bump a gate up to add
|
system with that logic. You don't add gates , you bump a gate up to add
|
an extra input.<br>
|
an extra input.<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<h3 class="western">A component must perform reset in one clock
|
<h3 class="western">A component must perform reset in one clock
|
cycle<br>
|
cycle<br>
|
</h3>
|
</h3>
|
The power on reset is really a slow operation. A typical system
|
The power on reset is really a slow operation. A typical system
|
could see:<br>
|
could see:<br>
|
<br>
|
<br>
|
<ul>
|
<ul>
|
<li>Ramp time for power rails</li>
|
<li>Ramp time for power rails</li>
|
<li>clock start up time</li>
|
<li>clock start up time</li>
|
<li>pll lock time</li>
|
<li>pll lock time</li>
|
</ul>
|
</ul>
|
You are looking at activity that is measured in the milliseconds on a
|
You are looking at activity that is measured in the milliseconds on a
|
system clock that is measured in the nanoseconds. Performing a reset in
|
system clock that is measured in the nanoseconds. Performing a reset in
|
one clock cycle requires adding logic to every single flipflop<br>
|
one clock cycle requires adding logic to every single flipflop<br>
|
for no good reason. A designer should only add reset logic as a last
|
for no good reason. A designer should only add reset logic as a last
|
resort. The prefered method is to use the existing mission mode logic
|
resort. The preferred method is to use the existing mission mode logic
|
to perform the reset. If you have a computational block with a fifty
|
to perform the reset. If you have a computational block with a fifty
|
stage deep pipeline then reset should force it's inputs to 0 and open
|
stage deep pipeline then reset should force it's inputs to 0 and open
|
all the gates so that every flipflop will be flushed out in 50 clocks.
|
all the gates so that every flipflop will be flushed out in 50 clocks.
|
Better yet would be to have the block feeding your input force it's
|
Better yet would be to have the block feeding your input force it's
|
output to all 0's during reset.<br>
|
output to all 0's during reset.<br>
|
<br>
|
<br>
|
Every design should spec a multicycle reset and give the designers the
|
Every design should spec a multicycle reset and give the designers the
|
freedom to reset any way they want as long as it's finished by the end
|
freedom to reset any way they want as long as it's finished by the end
|
of the reset pulse.<br>
|
of the reset pulse.<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
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<br>
|
<br>
|
<br>
|
<br>
|
<div id="toc__header" dir="ltr">
|
<div id="toc__header" dir="ltr">
|
<p><br>
|
<p><br>
|
</p>
|
</p>
|
</div>
|
</div>
|
<h1><a name="socgen_project"></a>How to design the Reset System<br>
|
<h1><a name="socgen_project"></a>How to design the Reset System<br>
|
</h1>
|
</h1>
|
<br>
|
<br>
|
<br>
|
<br>
|
<h3 class="western">1) Write a mission statement<br>
|
<h3 class="western">1) Write a mission statement<br>
|
</h3>
|
</h3>
|
The first step in any design task is to write a statement that sums up
|
The first step in any design task is to write a statement that sums up
|
what the thing you are designing will do. This is important
|
what the thing you are designing will do. This is important
|
because everything after this point must be traceable back to this
|
because everything after this point must be traceable back to this
|
statement. The statement will tell you what
|
statement. The statement will tell you what
|
steps you must follow. Anything that you cannot trace back to something
|
steps you must follow. Anything that you cannot trace back to something
|
in the mission statement is not part of the design<br>
|
in the mission statement is not part of the design<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
The mission statement for the reset system is:<br>
|
The mission statement for the reset system is:<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
The reset system will force all the nodes in a system or subsystem into
|
The reset system will force all the nodes in a system or subsystem into
|
a known good state while a reset trigger is active.<br>
|
a known good state while a reset trigger is active.<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<h3 class="western">2) Define the reset triggers<br>
|
<h3 class="western">2) Define the reset triggers<br>
|
</h3>
|
</h3>
|
We must now make a list of all the events that will cause us to reset
|
We must now make a list of all the events that will cause us to reset
|
all or part of the system. Our list is:<br>
|
all or part of the system. Our list is:<br>
|
<br>
|
<br>
|
<ul>
|
<ul>
|
<li>The design has a power monitor chip that provides a low signal
|
<li>The design has a power monitor chip that provides a low signal
|
when the supply rails have not been above the limit for a long
|
when the supply rails have not been above the limit for a long
|
enough period of time</li>
|
enough period of time</li>
|
</ul>
|
</ul>
|
<ul>
|
<ul>
|
<li>The design has a soft reset block that can reset any subblock if
|
<li>The design has a soft reset block that can reset any sub block if
|
its reset flop is set to 1.</li>
|
its reset flop is set to 1.</li>
|
</ul>
|
</ul>
|
<ul>
|
<ul>
|
<li>The clocks must run during reset but the divider has a special
|
<li>The clocks must run during reset but the divider has a special
|
reset input for simulation and testing</li>
|
reset input for simulation and testing</li>
|
</ul>
|
</ul>
|
<ul>
|
<ul>
|
<li>The design has ieee 1149.1 test logic with a active low trst* pin.</li>
|
<li>The design has ieee 1149.1 test logic with a active low trst* pin.</li>
|
</ul>
|
</ul>
|
<ul>
|
<ul>
|
<li>The reset signal has a metastable filter to sync it with
|
<li>The reset signal has a metastable filter to sync it with
|
the clock.<br>
|
the clock.<br>
|
</li>
|
</li>
|
</ul>
|
</ul>
|
The last is important because some designers will forget that the
|
The last is important because some designers will forget that the
|
filtered output is actually it's own seperate reset domain<br>
|
filtered output is actually it's own separate reset domain<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<h3 class="western">3) Define a known good state<br>
|
<h3 class="western">3) Define a known good state<br>
|
</h3>
|
</h3>
|
We now look at every storage element in the design and define a
|
We now look at every storage element in the design and define a
|
safe state for each element of either 1 or 0. Don't cares are not
|
safe state for each element of either 1 or 0. Don't cares are not
|
allowed. If you cannot pick a value then one will be assigned for you.
|
allowed. If you cannot pick a value then one will be assigned for you.
|
This task is best performed after the system and board designers have
|
This task is best performed after the system and board designers have
|
defined the known good state for the PCA. They will define the
|
defined the known good state for the PCA. They will define the
|
state for all of the pads, the ic design team must define the states
|
state for all of the pads, the ic design team must define the states
|
for all internal nodes.<br>
|
for all internal nodes.<br>
|
<br>
|
<br>
|
<h3 class="western">4) Assign storage elements to triggers<br>
|
<h3 class="western">4) Assign storage elements to triggers<br>
|
</h3>
|
</h3>
|
Once we have a list of all storage element we list any and all triggers
|
Once we have a list of all storage element we list any and all triggers
|
that will force them into a safe mode.<br>
|
that will force them into a safe mode.<br>
|
A typical list would list all the flipflops in timer module u12.r567
|
A typical list would list all the flipflops in timer module u12.r567
|
would be reset by:<br>
|
would be reset by:<br>
|
<br>
|
<br>
|
<ul>
|
<ul>
|
<li>an active high on soft reset bit #23</li>
|
<li>an active high on soft reset bit #23</li>
|
</ul>
|
</ul>
|
<ul>
|
<ul>
|
<li>an active low on the power monitor input</li>
|
<li>an active low on the power monitor input</li>
|
</ul>
|
</ul>
|
<ul>
|
<ul>
|
<li>an active low on the simulation/test reset</li>
|
<li>an active low on the simulation/test reset</li>
|
</ul>
|
</ul>
|
<ul>
|
<ul>
|
<li>an active low on the output of the metastable filter</li>
|
<li>an active low on the output of the metastable filter</li>
|
</ul>
|
</ul>
|
<br>
|
<br>
|
The jtag reset is not included because it doesnt reset the timer.
|
The jtag reset is not included because it doesn't reset the
|
|
timer.
|
Once this step is complete it will provide a map for the reset
|
Once this step is complete it will provide a map for the reset
|
distribution tree that you will need. The best way to distribute the
|
distribution tree that you will need. The best way to distribute the
|
reset over a large design is to use what is called a "synchronous reset
|
reset over a large design is to use what is called a "synchronous reset
|
tree".<br>
|
tree".<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<h3 class="western">5) Select between synchronous or asynchronous reset
|
<h3 class="western">5) Select between synchronous or asynchronous reset
|
system<br>
|
system<br>
|
</h3>
|
</h3>
|
At this point it is easy to see if we need a synchronous or
|
At this point it is easy to see if we need a synchronous or
|
asynchronous reset system. If your trigger is asynchronous then you
|
asynchronous reset system. If your trigger is asynchronous then you
|
must design a asynchronous reset system. If the trigger can occur
|
must design a asynchronous reset system. If the trigger can occur
|
without a clock then you must be able to reset the system without a
|
without a clock then you must be able to reset the system without a
|
clock.<br>
|
clock.<br>
|
<br>
|
<br>
|
If the trigger is synchronous then you may design a synchronous reset
|
If the trigger is synchronous then you may design a synchronous reset
|
system or you may also choose to design a asynchronous one. The
|
system or you may also choose to design a asynchronous one. The
|
async one will enter reset one cycle before the sync one
|
async one will enter reset one cycle before the sync one
|
but they will both exit on at the same time. <br>
|
but they will both exit on at the same time. <br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
|
<h3 class="western">6) Select reset style for each flip/flop<br>
|
|
</h3>
|
|
We now need to select a reset "Style" for each flip/flop from the four
|
|
possible reset styles.<br>
|
|
<br>
|
|
<br>
|
|
<ul>
|
|
<li>Synchronous</li>
|
|
<li>Synchronous with output override</li>
|
|
<li>Asynchronous</li>
|
|
<li>Both Synchronous and Asynchronous</li>
|
|
</ul>
|
<br>
|
<br>
|
|
If the reset system is synchronous then you may choose any of the four
|
|
styles. If it is asynchronous then you cannot use the synchronous style.<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
|
<img style="width: 800px; height: 600px;" alt=""
|
|
src="../png/reset_fig1.png"><br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
|
<h3 class="western">7) Apply DFT fixes to all asynchronous ports<br>
|
|
</h3>
|
|
All paths from the Q output of a flip/flop to the asynchronous
|
|
reset/preset port of a flip/flop must be disabled during scan testing.
|
|
The use of a test mux to do this is not recommended because anytime you
|
|
use a test mux you are not testing the circuit as it is used in mission
|
|
mode. There will always be at least one point of failure inside the
|
|
test mux where scan tests will pass but the IC will not function.<br>
|
|
<br>
|
|
The recommended method is to gate off the synchronous path with a atg
|
|
test signal and then recombine it with an asynchronous reset so that
|
|
the async reset it self is still testable. The lib module
|
|
cde_asyncdisable is available for this purpose. DO NOT CREATE YOUR OWN
|
|
TEST LOGIC. Checking the rtl code to ensure that all asynchronous
|
|
resets are testable requires a fairly sophisticated and expensive tool.
|
|
Checking the rtl to ensure that all asynchronous resets are properly
|
|
connected to a cde_asyncdisable module takes a simple perl script.<br>
|
|
<br>
|
|
<br>
|
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
<br>
|
|
<img style="width: 800px; height: 600px;" alt=""
|
|
src="../png/reset_fig2.png"><br>
|
<br>
|
<br>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
<p><br>
|
<p><br>
|
<br>
|
<br>
|
</p>
|
</p>
|
</body>
|
</body>
|
</html>
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</html>
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