eval 'exec `which perl` -S $0 ${1+"$@"}'
|
eval 'exec `which perl` -S $0 ${1+"$@"}'
|
if 0;
|
if 0;
|
|
|
#/**********************************************************************/
|
#/****************************************************************************/
|
#/* */
|
|
#/* ------- */
|
|
#/* / SOC \ */
|
|
#/* / GEN \ */
|
|
#/* / TOOL \ */
|
|
#/* ============== */
|
|
#/* | | */
|
|
#/* |____________| */
|
|
#/* */
|
#/* */
|
|
#/* SOCGEN Design for Reuse toolset */
|
#/* */
|
#/* */
|
|
#/* Version 1.0.0 */
|
#/* */
|
#/* */
|
#/* Author(s): */
|
#/* Author(s): */
|
#/* - John Eaton, jt_eaton@opencores.org */
|
#/* - John Eaton, z3qmtr45@gmail.com */
|
#/* */
|
#/* */
|
#/**********************************************************************/
|
#/****************************************************************************/
|
#/* */
|
#/* */
|
#/* Copyright (C) <2010-2013> */
|
|
#/* */
|
#/* */
|
#/* This source file may be used and distributed without */
|
#/* Copyright 2016 John T Eaton */
|
#/* restriction provided that this copyright statement is not */
|
|
#/* removed from the file and that any derivative work contains */
|
|
#/* the original copyright notice and the associated disclaimer. */
|
|
#/* */
|
|
#/* This source file is free software; you can redistribute it */
|
|
#/* and/or modify it under the terms of the GNU Lesser General */
|
|
#/* Public License as published by the Free Software Foundation; */
|
|
#/* either version 2.1 of the License, or (at your option) any */
|
|
#/* later version. */
|
|
#/* */
|
|
#/* This source is distributed in the hope that it will be */
|
|
#/* useful, but WITHOUT ANY WARRANTY; without even the implied */
|
|
#/* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR */
|
|
#/* PURPOSE. See the GNU Lesser General Public License for more */
|
|
#/* details. */
|
|
#/* */
|
|
#/* You should have received a copy of the GNU Lesser General */
|
|
#/* Public License along with this source; if not, download it */
|
|
#/* from http://www.opencores.org/lgpl.shtml */
|
|
#/* */
|
#/* */
|
#/**********************************************************************/
|
#/* Licensed under the Apache License, Version 2.0 (the "License"); */
|
|
#/* you may not use this file except in compliance with the License. */
|
|
#/* You may obtain a copy of the License at */
|
|
#/* */
|
|
#/* http://www.apache.org/licenses/LICENSE-2.0 */
|
|
#/* */
|
|
#/* Unless required by applicable law or agreed to in writing, software */
|
|
#/* distributed under the License is distributed on an "AS IS" BASIS, */
|
|
#/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. */
|
|
#/* See the License for the specific language governing permissions and */
|
|
#/* limitations under the License. */
|
|
#/* */
|
|
#/* */
|
|
#/****************************************************************************/
|
|
|
|
|
############################################################################
|
############################################################################
|
# General PERL config
|
# General PERL config
|
############################################################################
|
############################################################################
|
use Getopt::Long;
|
use Getopt::Long;
|
use English;
|
use English;
|
use File::Basename;
|
use File::Basename;
|
use Cwd;
|
use Cwd;
|
use XML::LibXML;
|
use XML::LibXML;
|
use lib './tools';
|
use lib './tools';
|
use sys::lib;
|
use sys::lib;
|
use yp::lib;
|
use yp::lib;
|
use BerkeleyDB;
|
use BerkeleyDB;
|
use Parallel::ForkManager;
|
use Parallel::ForkManager;
|
|
|
$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
|
$OUTPUT_AUTOFLUSH = 1; # set autoflush of stdout to TRUE.
|
|
|
|
|
############################################################################
|
############################################################################
|
### Process the options
|
### Process the options
|
############################################################################
|
############################################################################
|
Getopt::Long::config("require_order", "prefix=-");
|
Getopt::Long::config("require_order", "prefix=-");
|
GetOptions("h","help",
|
GetOptions("h","help",
|
) || die "(use '$program_name -h' for help)";
|
) || die "(use '$program_name -h' for help)";
|
|
|
|
|
|
|
|
|
##############################################################################
|
##############################################################################
|
## Help option
|
## Help option
|
##############################################################################
|
##############################################################################
|
if ( $opt_h or $opt_help )
|
if ( $opt_h or $opt_help )
|
{ print "\n build_elab_master";
|
{ print "\n build_elab_master";
|
print "\n";
|
print "\n";
|
exit 1;
|
exit 1;
|
}
|
}
|
|
|
|
|
my $parser = XML::LibXML->new();
|
my $parser = XML::LibXML->new();
|
|
|
|
|
|
|
|
|
#/**********************************************************************/
|
#/**********************************************************************/
|
#/* Process each library by finding any ip-xact file in any component */
|
#/* Process each library by finding any ip-xact file in any component */
|
#/* */
|
#/* */
|
#/* Each ip-xact file is parsed and it's filename and the names of any*/
|
#/* Each ip-xact file is parsed and it's filename and the names of any*/
|
#/* modules that it uses are saved. */
|
#/* modules that it uses are saved. */
|
#/* */
|
#/* */
|
#/* */
|
#/* */
|
#/**********************************************************************/
|
#/**********************************************************************/
|
|
|
my @elab_cmds = ();
|
my @elab_cmds = ();
|
my @des_cmds = ();
|
my @des_cmds = ();
|
my @gen_cmds = ();
|
my @gen_cmds = ();
|
my @top_levels =();
|
my @top_levels =();
|
my @children =();
|
my @children =();
|
|
|
|
|
print "Build_elab_master \n";
|
print "Build_elab_master \n";
|
|
|
my $number_of_cpus = yp::lib::get_number_of_cpus();
|
my $number_of_cpus = yp::lib::get_number_of_cpus();
|
|
|
my $home = cwd();
|
my $home = cwd();
|
|
|
my $prefix = yp::lib::get_workspace();
|
my $prefix = yp::lib::get_workspace();
|
$prefix = "/${prefix}";
|
$prefix = "/${prefix}";
|
|
|
my @vendors = yp::lib::find_vendors();
|
my @vendors = yp::lib::find_vendors();
|
|
|
foreach my $vendor (@vendors)
|
foreach my $vendor (@vendors)
|
{
|
{
|
|
|
my $vendor_status = yp::lib::get_vendor_status($vendor);
|
my $vendor_status = yp::lib::get_vendor_status($vendor);
|
if($vendor_status eq "active")
|
if($vendor_status eq "active")
|
{
|
{
|
my @libraries = yp::lib::find_libraries($vendor);
|
my @libraries = yp::lib::find_libraries($vendor);
|
foreach my $library (@libraries)
|
foreach my $library (@libraries)
|
{
|
{
|
|
|
my $library_status = yp::lib::get_library_status($vendor,$library);
|
my $library_status = yp::lib::get_library_status($vendor,$library);
|
if($library_status eq "active")
|
if($library_status eq "active")
|
{
|
{
|
|
|
|
|
|
|
|
|
|
|
|
|
my @components = yp::lib::find_components($vendor,$library);
|
my @components = yp::lib::find_components($vendor,$library);
|
|
|
foreach my $component (@components)
|
foreach my $component (@components)
|
{
|
{
|
my $socgen_filename = yp::lib::find_componentConfiguration($vendor,$library,$component);
|
my $socgen_filename = yp::lib::find_componentConfiguration($vendor,$library,$component);
|
if($socgen_filename)
|
if($socgen_filename)
|
{
|
{
|
my $socgen_file = $parser->parse_file($socgen_filename);
|
my $socgen_file = $parser->parse_file($socgen_filename);
|
|
|
|
|
|
|
#/*********************************************************************************************/
|
#/*********************************************************************************************/
|
#/ elaborate each testbench */
|
#/ elaborate each testbench */
|
#/ */
|
#/ */
|
#/*********************************************************************************************/
|
#/*********************************************************************************************/
|
|
|
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))
|
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))
|
{
|
{
|
|
|
my $testbench_variant = $j_name ->findnodes('./text()')->to_literal ;
|
my $testbench_variant = $j_name ->findnodes('./text()')->to_literal ;
|
my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
|
my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
|
my $testbench_config = $j_name ->findnodes('../socgen:configuration/text()')->to_literal ;
|
my $testbench_config = $j_name ->findnodes('../socgen:configuration/text()')->to_literal ;
|
my $testbench_instance = $j_name ->findnodes('../socgen:bus/socgen:instance/text()')->to_literal ;
|
my $testbench_instance = $j_name ->findnodes('../socgen:bus/socgen:instance/text()')->to_literal ;
|
my $testbench_bus_name = $j_name ->findnodes('../socgen:bus/socgen:bus_name/text()')->to_literal ;
|
my $testbench_bus_name = $j_name ->findnodes('../socgen:bus/socgen:bus_name/text()')->to_literal ;
|
|
|
|
|
if(defined $testbench_config && length $testbench_config > 0)
|
if(defined $testbench_config && length $testbench_config > 0)
|
{
|
{
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -configuration ${testbench_config} \n";
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -configuration ${testbench_config} \n";
|
}
|
}
|
else
|
else
|
{
|
{
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n";
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n";
|
}
|
}
|
|
|
|
|
push @elab_cmds, $cmd;
|
push @elab_cmds, $cmd;
|
|
|
$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n ";
|
$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n ";
|
push @gen_cmds, $cmd;
|
push @gen_cmds, $cmd;
|
|
|
$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n ";
|
$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} \n ";
|
push @des_cmds, $cmd;
|
push @des_cmds, $cmd;
|
|
|
if ($testbench_instance)
|
if ($testbench_instance)
|
{
|
{
|
$cmd ="./tools/verilog/trace_bus -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -path $testbench_instance -bus_name $testbench_bus_name ";
|
$cmd ="./tools/verilog/trace_bus -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -path $testbench_instance -bus_name $testbench_bus_name ";
|
|
|
push @gen_cmds, $cmd;
|
push @gen_cmds, $cmd;
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
#/*********************************************************************************************/
|
#/*********************************************************************************************/
|
#/ elaborate for each test */
|
#/ elaborate for each test */
|
#/ */
|
#/ */
|
#/*********************************************************************************************/
|
#/*********************************************************************************************/
|
|
|
foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:icarus/socgen:test/socgen:name"))
|
foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:icarus/socgen:test/socgen:name"))
|
{
|
{
|
my $test_name = $i_name ->findnodes('./text()')->to_literal ;
|
my $test_name = $i_name ->findnodes('./text()')->to_literal ;
|
my $test_variant = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
|
my $test_variant = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
|
|
|
# print "XXXX $vendor $library $component $test_variant $test_name \n ";
|
# print "XXXX $vendor $library $component $test_variant $test_name \n ";
|
|
|
|
|
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))
|
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))
|
{
|
{
|
my $testbench_variant = $j_name ->findnodes('./text()')->to_literal ;
|
my $testbench_variant = $j_name ->findnodes('./text()')->to_literal ;
|
my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
|
my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
|
my $testbench_instance = $j_name ->findnodes('../socgen:bus/socgen:instance/text()')->to_literal ;
|
my $testbench_instance = $j_name ->findnodes('../socgen:bus/socgen:instance/text()')->to_literal ;
|
my $testbench_bus_name = $j_name ->findnodes('../socgen:bus/socgen:bus_name/text()')->to_literal ;
|
my $testbench_bus_name = $j_name ->findnodes('../socgen:bus/socgen:bus_name/text()')->to_literal ;
|
|
|
|
|
if($test_variant eq $testbench_variant )
|
if($test_variant eq $testbench_variant )
|
{
|
{
|
# print "YYYY $prefix $vendor $library $component $testbench_version $test_name \n ";
|
# print "YYYY $prefix $vendor $library $component $testbench_version $test_name \n ";
|
|
|
#print "ELAB_XXXXX test_variant $vendor $library \n";
|
#print "ELAB_XXXXX test_variant $vendor $library \n";
|
|
|
push @top_levels, "${vendor}::${library}::${component}::${testbench_version}::${test_name}";
|
push @top_levels, "${vendor}::${library}::${component}::${testbench_version}::${test_name}";
|
|
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -env sim -tool icarus -unit test -name $test_name \n";
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -env sim -tool icarus -unit test -name $test_name \n";
|
|
|
push @elab_cmds, $cmd;
|
push @elab_cmds, $cmd;
|
|
|
|
|
|
|
$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -name $test_name \n";
|
$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -name $test_name \n";
|
|
|
push @gen_cmds, $cmd;
|
push @gen_cmds, $cmd;
|
|
|
$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -name $test_name \n";
|
$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -name $test_name \n";
|
|
|
push @des_cmds, $cmd;
|
push @des_cmds, $cmd;
|
|
|
|
|
|
|
|
|
if ($testbench_instance)
|
if ($testbench_instance)
|
{
|
{
|
|
|
$cmd ="./tools/verilog/trace_bus -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -path $testbench_instance -bus_name $testbench_bus_name -test_name $test_name ";
|
$cmd ="./tools/verilog/trace_bus -prefix ${prefix} -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -path $testbench_instance -bus_name $testbench_bus_name -test_name $test_name ";
|
|
|
push @gen_cmds, $cmd;
|
push @gen_cmds, $cmd;
|
}
|
}
|
}
|
}
|
|
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#/*********************************************************************************************/
|
#/*********************************************************************************************/
|
#/ elaborate for each chip */
|
#/ elaborate for each chip */
|
#/ */
|
#/ */
|
#/*********************************************************************************************/
|
#/*********************************************************************************************/
|
|
|
foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:ise/socgen:chip/socgen:name"))
|
foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:fpgas/socgen:fpga/socgen:name"))
|
{
|
{
|
my $chip_name = $i_name ->findnodes('./text()')->to_literal ;
|
my $chip_name = $i_name ->findnodes('./text()')->to_literal ;
|
my $chip_variant = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
|
my $chip_variant = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
|
|
|
# print "XXXX $vendor $library $component $chip_variant $chip_name \n ";
|
# print "XXXX $vendor $library $component $chip_variant $chip_name \n ";
|
|
|
|
|
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:fpgas/socgen:fpga/socgen:variant"))
|
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:syn/socgen:fpgas/socgen:fpga/socgen:variant"))
|
{
|
{
|
my $fpga_variant = $j_name ->findnodes('./text()')->to_literal ;
|
my $fpga_variant = $j_name ->findnodes('./text()')->to_literal ;
|
my $fpga_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
|
my $fpga_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
|
|
|
|
|
if($chip_variant eq $fpga_variant )
|
if($chip_variant eq $fpga_variant )
|
{
|
{
|
# print "YYYY $prefix $vendor $library $component $fpga_version $chip_name \n ";
|
# print "YYYY $prefix $vendor $library $component $fpga_version $chip_name \n ";
|
|
|
#print "ELAB_XXXXX test_variant $vendor $library \n";
|
#print "ELAB_XXXXX test_variant $vendor $library \n";
|
|
|
push @top_levels, "${vendor}::${library}::${component}::${fpga_version}::${chip_name}";
|
push @top_levels, "${vendor}::${library}::${component}::${fpga_version}::${chip_name}";
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -env syn -tool ise -unit chip -name $chip_name \n";
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -env syn -tool ise -unit chip -name $chip_name \n";
|
|
|
push @elab_cmds, $cmd;
|
push @elab_cmds, $cmd;
|
|
|
|
|
|
|
$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -name $chip_name \n";
|
$cmd ="./tools/verilog/gen_root -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -name $chip_name \n";
|
|
|
push @gen_cmds, $cmd;
|
push @gen_cmds, $cmd;
|
|
|
$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -name $chip_name \n";
|
$cmd ="./tools/verilog/gen_design -vendor ${vendor} -library ${library} -component ${component} -version ${fpga_version} -name $chip_name \n";
|
|
|
push @des_cmds, $cmd;
|
push @des_cmds, $cmd;
|
}
|
}
|
|
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#/*********************************************************************************************/
|
#/*********************************************************************************************/
|
#/ elaborate for each rtlcheck */
|
#/ elaborate for each rtlcheck */
|
#/ */
|
#/ */
|
#/*********************************************************************************************/
|
#/*********************************************************************************************/
|
|
|
foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:rtl_check/socgen:lint/socgen:name"))
|
foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:rtl_check/socgen:lint/socgen:name"))
|
{
|
{
|
my $lint_name = $i_name ->findnodes('./text()')->to_literal ;
|
my $lint_name = $i_name ->findnodes('./text()')->to_literal ;
|
my $lint_variant = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
|
my $lint_variant = $i_name ->findnodes('../socgen:variant/text()')->to_literal ;
|
|
|
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))
|
foreach my $j_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:sim/socgen:testbenches/socgen:testbench/socgen:variant"))
|
{
|
{
|
my $testbench_variant = $j_name ->findnodes('./text()')->to_literal ;
|
my $testbench_variant = $j_name ->findnodes('./text()')->to_literal ;
|
my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
|
my $testbench_version = $j_name ->findnodes('../socgen:version/text()')->to_literal ;
|
|
|
if($lint_variant eq $testbench_variant )
|
if($lint_variant eq $testbench_variant )
|
{
|
{
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -env sim -tool rtl_check -unit lint -name $lint_name \n";
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${testbench_version} -env sim -tool rtl_check -unit lint -name $lint_name \n";
|
push @elab_cmds, $cmd;
|
push @elab_cmds, $cmd;
|
}
|
}
|
|
|
}
|
}
|
}
|
}
|
|
|
|
|
#/**********************************************************************************************/
|
#/**********************************************************************************************/
|
#/ elaborate for each top module */
|
#/ elaborate for each top module */
|
#/ */
|
#/ */
|
#/*********************************************************************************************/
|
#/*********************************************************************************************/
|
|
|
foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:configurations/socgen:configuration/socgen:version"))
|
foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:configurations/socgen:configuration/socgen:version"))
|
{
|
{
|
my $version_name = $i_name ->findnodes('./text()')->to_literal ;
|
my $version_name = $i_name ->findnodes('./text()')->to_literal ;
|
my $configuration = $i_name ->findnodes('../socgen:name/text()')->to_literal ;
|
my $configuration = $i_name ->findnodes('../socgen:name/text()')->to_literal ;
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${version_name} -configuration ${configuration}\n";
|
$cmd ="./tools/verilog/elab_verilog -vendor ${vendor} -library ${library} -component ${component} -version ${version_name} -configuration ${configuration}\n";
|
push @elab_cmds, $cmd;
|
push @elab_cmds, $cmd;
|
}
|
}
|
|
|
|
|
}
|
}
|
|
|
|
|
|
|
}
|
}
|
|
|
|
|
|
|
|
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
|
|
|
|
@elab_cmds = sys::lib::trim_sort(@elab_cmds);
|
@elab_cmds = sys::lib::trim_sort(@elab_cmds);
|
|
|
print "Start elab_cmds \n";
|
print "Start elab_cmds \n";
|
|
|
foreach $cmd (@elab_cmds)
|
foreach $cmd (@elab_cmds)
|
{
|
{
|
|
|
# $manager->start and next;
|
# $manager->start and next;
|
#print "$cmd";
|
#print "$cmd";
|
if (system($cmd)) {}
|
if (system($cmd)) {}
|
# $manager->finish;
|
# $manager->finish;
|
}
|
}
|
|
|
|
|
print "End elab_cmds \n";
|
print "End elab_cmds \n";
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
@top_levels = sys::lib::trim_sort(@top_levels);
|
@top_levels = sys::lib::trim_sort(@top_levels);
|
|
|
|
|
foreach $level (@top_levels)
|
foreach $level (@top_levels)
|
{
|
{
|
|
|
( $ven,$lib,$cmp,$ver,$nam) = split( /\::/ , $level);
|
( $ven,$lib,$cmp,$ver,$nam) = split( /\::/ , $level);
|
|
|
my $elab_db_filename = yp::lib::get_elab_db_filename($ven,$lib,$cmp,$ver,"default");
|
my $elab_db_filename = yp::lib::get_elab_db_filename($ven,$lib,$cmp,$ver,"default");
|
|
|
my $elab_db = new BerkeleyDB::Hash( -Filename => "$elab_db_filename", -Flags => DB_CREATE ) or die "Cannot open $elab_db_filename: $!";
|
my $elab_db = new BerkeleyDB::Hash( -Filename => "$elab_db_filename", -Flags => DB_CREATE ) or die "Cannot open $elab_db_filename: $!";
|
|
|
my $key;
|
my $key;
|
my $value;
|
my $value;
|
|
|
$cursor = $elab_db ->db_cursor() ;
|
$cursor = $elab_db ->db_cursor() ;
|
while ($cursor->c_get($key, $value, DB_NEXT) == 0)
|
while ($cursor->c_get($key, $value, DB_NEXT) == 0)
|
{
|
{
|
|
|
# print "$key \n";
|
# print "$key \n";
|
my $VLNV;
|
my $VLNV;
|
my $vlnv;
|
my $vlnv;
|
|
|
|
|
( ${VLNV},${vlnv}) = split( /___root./ , $key);
|
( ${VLNV},${vlnv}) = split( /___root./ , $key);
|
if($VLNV eq "component")
|
if($VLNV eq "component")
|
{
|
{
|
if($vlnv)
|
if($vlnv)
|
{
|
{
|
push @children,$value;
|
push @children,$value;
|
|
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
@children = sys::lib::trim_sort(@children);
|
@children = sys::lib::trim_sort(@children);
|
|
|
foreach my $child (@children)
|
foreach my $child (@children)
|
{
|
{
|
my $ven;
|
my $ven;
|
my $lib;
|
my $lib;
|
my $cmp;
|
my $cmp;
|
my $ver;
|
my $ver;
|
( ${ven},${lib},${cmp},${ver}) = split( /:/ , $child);
|
( ${ven},${lib},${cmp},${ver}) = split( /:/ , $child);
|
|
|
|
|
|
|
my $child_filename = yp::lib::find_componentConfiguration($ven,$lib,$cmp);
|
my $child_filename = yp::lib::find_componentConfiguration($ven,$lib,$cmp);
|
if($child_filename)
|
if($child_filename)
|
{
|
{
|
my $socgen_file = $parser->parse_file($child_filename);
|
my $socgen_file = $parser->parse_file($child_filename);
|
foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:configurations/socgen:configuration/socgen:version"))
|
foreach my $i_name ($socgen_file->findnodes("//socgen:componentConfiguration/socgen:configurations/socgen:configuration/socgen:version"))
|
{
|
{
|
my $version_name = $i_name ->findnodes('./text()')->to_literal ;
|
my $version_name = $i_name ->findnodes('./text()')->to_literal ;
|
my $configuration = $i_name ->findnodes('../socgen:name/text()')->to_literal ;
|
my $configuration = $i_name ->findnodes('../socgen:name/text()')->to_literal ;
|
$cmd ="./tools/verilog/elab_verilog -vendor ${ven} -library ${lib} -component ${cmp} -version ${version_name} -configuration ${configuration}\n";
|
$cmd ="./tools/verilog/elab_verilog -vendor ${ven} -library ${lib} -component ${cmp} -version ${version_name} -configuration ${configuration}\n";
|
|
|
if (system($cmd)) {}
|
if (system($cmd)) {}
|
}
|
}
|
}
|
}
|
}
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
@des_cmds = sys::lib::trim_sort(@des_cmds);
|
@des_cmds = sys::lib::trim_sort(@des_cmds);
|
@gen_cmds = sys::lib::trim_sort(@gen_cmds);
|
@gen_cmds = sys::lib::trim_sort(@gen_cmds);
|
|
|
|
|
#print "Execute cmds \n";
|
#print "Execute cmds \n";
|
|
|
my $manager = new Parallel::ForkManager( $number_of_cpus );
|
my $manager = new Parallel::ForkManager( $number_of_cpus );
|
|
|
|
|
|
|
|
|
#$manager->wait_all_children;
|
#$manager->wait_all_children;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
foreach $cmd (@des_cmds)
|
foreach $cmd (@des_cmds)
|
{
|
{
|
if (system($cmd)) {}
|
if (system($cmd)) {}
|
}
|
}
|
|
|
print "End des_cmds \n";
|
print "End des_cmds \n";
|
|
|
foreach $cmd (@gen_cmds)
|
foreach $cmd (@gen_cmds)
|
{
|
{
|
# $manager->start and next;
|
# $manager->start and next;
|
if (system($cmd)) {}
|
if (system($cmd)) {}
|
# $manager->finish;
|
# $manager->finish;
|
}
|
}
|
|
|
#$manager->wait_all_children;
|
#$manager->wait_all_children;
|
|
|
print "End All \n";
|
print "End All \n";
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
