--altddio_out CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" INVERT_OUTPUT="OFF" POWER_UP_HIGH="OFF" WIDTH=1 datain_h datain_l dataout outclock
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--altddio_out CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" INVERT_OUTPUT="OFF" POWER_UP_HIGH="OFF" WIDTH=1 datain_h datain_l dataout outclock
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--VERSION_BEGIN 17.0 cbx_altddio_out 2017:06:01:09:22:16:SJ cbx_cycloneii 2017:06:01:09:22:16:SJ cbx_maxii 2017:06:01:09:22:16:SJ cbx_mgl 2017:06:01:10:52:00:SJ cbx_stratix 2017:06:01:09:22:16:SJ cbx_stratixii 2017:06:01:09:22:16:SJ cbx_stratixiii 2017:06:01:09:22:16:SJ cbx_stratixv 2017:06:01:09:22:16:SJ cbx_util_mgl 2017:06:01:09:22:16:SJ VERSION_END
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--VERSION_BEGIN 17.1 cbx_altddio_out 2017:12:05:11:11:27:SJ cbx_cycloneii 2017:12:05:11:11:27:SJ cbx_maxii 2017:12:05:11:11:27:SJ cbx_mgl 2017:12:05:12:41:31:SJ cbx_stratix 2017:12:05:11:11:27:SJ cbx_stratixii 2017:12:05:11:11:27:SJ cbx_stratixiii 2017:12:05:11:11:27:SJ cbx_stratixv 2017:12:05:11:11:27:SJ cbx_util_mgl 2017:12:05:11:11:27:SJ VERSION_END
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-- Copyright (C) 2017 Intel Corporation. All rights reserved.
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-- Copyright (C) 2017 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel MegaCore Function License Agreement, or other
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- applicable license agreement, including, without limitation,
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-- agreement, including, without limitation, that your use is for
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-- that your use is for the sole purpose of programming logic
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-- the sole purpose of programming logic devices manufactured by
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-- devices manufactured by Intel and sold by Intel or its
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-- Intel and sold by Intel or its authorized distributors. Please
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-- authorized distributors. Please refer to the applicable
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-- refer to the applicable agreement for further details.
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-- agreement for further details.
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FUNCTION cyclonev_ddio_out (areset, clk, clkhi, clklo, datainhi, datainlo, ena, hrbypass, muxsel, sreset)
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FUNCTION cyclonev_ddio_out (areset, clk, clkhi, clklo, datainhi, datainlo, ena, hrbypass, muxsel, sreset)
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WITH ( async_mode, half_rate_mode, power_up, sync_mode, use_new_clocking_model)
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WITH ( async_mode, half_rate_mode, power_up, sync_mode, use_new_clocking_model)
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RETURNS ( dataout);
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RETURNS ( dataout);
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--synthesis_resources = IO 1
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--synthesis_resources = IO 1
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OPTIONS ALTERA_INTERNAL_OPTION = "ANALYZE_METASTABILITY=OFF;ADV_NETLIST_OPT_ALLOWED=DEFAULT";
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OPTIONS ALTERA_INTERNAL_OPTION = "ANALYZE_METASTABILITY=OFF;ADV_NETLIST_OPT_ALLOWED=DEFAULT";
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SUBDESIGN ddio_out_uqe
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SUBDESIGN ddio_out_uqe
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(
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(
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datain_h[0..0] : input;
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datain_h[0..0] : input;
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datain_l[0..0] : input;
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datain_l[0..0] : input;
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dataout[0..0] : output;
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dataout[0..0] : output;
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outclock : input;
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outclock : input;
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)
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)
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VARIABLE
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VARIABLE
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ddio_outa[0..0] : cyclonev_ddio_out
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ddio_outa[0..0] : cyclonev_ddio_out
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WITH (
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WITH (
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async_mode = "none",
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async_mode = "none",
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power_up = "low",
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power_up = "low",
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sync_mode = "none",
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sync_mode = "none",
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use_new_clocking_model = "true"
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use_new_clocking_model = "true"
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);
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);
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BEGIN
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BEGIN
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ddio_outa[].clkhi = outclock;
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ddio_outa[].clkhi = outclock;
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ddio_outa[].clklo = outclock;
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ddio_outa[].clklo = outclock;
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ddio_outa[].datainhi = datain_h[];
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ddio_outa[].datainhi = datain_h[];
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ddio_outa[].datainlo = datain_l[];
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ddio_outa[].datainlo = datain_l[];
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ddio_outa[].muxsel = outclock;
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ddio_outa[].muxsel = outclock;
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dataout[] = ddio_outa[].dataout;
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dataout[] = ddio_outa[].dataout;
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END;
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END;
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--VALID FILE
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--VALID FILE
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