Flow report for spw_fifo_ulight
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Flow report for spw_fifo_ulight
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Thu Aug 24 22:42:14 2017
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Fri Sep 15 08:19:20 2017
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Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition
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Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition
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---------------------
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---------------------
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; Table of Contents ;
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; Table of Contents ;
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---------------------
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---------------------
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1. Legal Notice
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1. Legal Notice
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2. Flow Summary
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2. Flow Summary
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3. Flow Settings
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3. Flow Settings
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4. Flow Non-Default Global Settings
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4. Flow Non-Default Global Settings
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5. Flow Elapsed Time
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5. Flow Elapsed Time
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6. Flow OS Summary
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6. Flow OS Summary
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7. Flow Log
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7. Flow Log
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8. Flow Messages
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8. Flow Messages
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9. Flow Suppressed Messages
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9. Flow Suppressed Messages
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----------------
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----------------
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; Legal Notice ;
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; Legal Notice ;
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----------------
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----------------
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Copyright (C) 2017 Intel Corporation. All rights reserved.
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Copyright (C) 2017 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel MegaCore Function License Agreement, or other
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the Intel MegaCore Function License Agreement, or other
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applicable license agreement, including, without limitation,
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applicable license agreement, including, without limitation,
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that your use is for the sole purpose of programming logic
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that your use is for the sole purpose of programming logic
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devices manufactured by Intel and sold by Intel or its
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devices manufactured by Intel and sold by Intel or its
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authorized distributors. Please refer to the applicable
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authorized distributors. Please refer to the applicable
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agreement for further details.
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agreement for further details.
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+-------------------------------------------------------------------------------+
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+-------------------------------------------------------------------------------+
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; Flow Summary ;
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; Flow Summary ;
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+---------------------------------+---------------------------------------------+
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+---------------------------------+---------------------------------------------+
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; Flow Status ; Successful - Thu Aug 24 22:42:14 2017 ;
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; Flow Status ; Successful - Fri Sep 15 08:19:20 2017 ;
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; Quartus Prime Version ; 17.0.1 Build 598 06/07/2017 SJ Lite Edition ;
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; Quartus Prime Version ; 17.0.1 Build 598 06/07/2017 SJ Lite Edition ;
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; Revision Name ; spw_fifo_ulight ;
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; Revision Name ; spw_fifo_ulight ;
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; Top-level Entity Name ; SPW_ULIGHT_FIFO ;
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; Top-level Entity Name ; SPW_ULIGHT_FIFO ;
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; Family ; Cyclone V ;
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; Family ; Cyclone V ;
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; Device ; 5CSEMA4U23C6 ;
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; Device ; 5CSEMA4U23C6 ;
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; Timing Models ; Final ;
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; Timing Models ; Final ;
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; Logic utilization (in ALMs) ; 2,724 / 15,880 ( 17 % ) ;
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; Logic utilization (in ALMs) ; 3,209 / 15,880 ( 20 % ) ;
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; Total registers ; 3603 ;
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; Total registers ; 4692 ;
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; Total pins ; 19 / 314 ( 6 % ) ;
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; Total pins ; 19 / 314 ( 6 % ) ;
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; Total virtual pins ; 0 ;
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; Total virtual pins ; 0 ;
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; Total block memory bits ; 1,152 / 2,764,800 ( < 1 % ) ;
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; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ;
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; Total DSP Blocks ; 0 / 84 ( 0 % ) ;
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; Total DSP Blocks ; 0 / 84 ( 0 % ) ;
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; Total HSSI RX PCSs ; 0 ;
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; Total HSSI RX PCSs ; 0 ;
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; Total HSSI PMA RX Deserializers ; 0 ;
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; Total HSSI PMA RX Deserializers ; 0 ;
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; Total HSSI TX PCSs ; 0 ;
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; Total HSSI TX PCSs ; 0 ;
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; Total HSSI PMA TX Serializers ; 0 ;
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; Total HSSI PMA TX Serializers ; 0 ;
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; Total PLLs ; 1 / 5 ( 20 % ) ;
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; Total PLLs ; 1 / 5 ( 20 % ) ;
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; Total DLLs ; 0 / 4 ( 0 % ) ;
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; Total DLLs ; 0 / 4 ( 0 % ) ;
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+---------------------------------+---------------------------------------------+
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+---------------------------------+---------------------------------------------+
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+-----------------------------------------+
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+-----------------------------------------+
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; Flow Settings ;
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; Flow Settings ;
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+-------------------+---------------------+
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+-------------------+---------------------+
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; Option ; Setting ;
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; Option ; Setting ;
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+-------------------+---------------------+
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+-------------------+---------------------+
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; Start date & time ; 08/24/2017 22:32:50 ;
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; Start date & time ; 09/15/2017 08:07:49 ;
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; Main task ; Compilation ;
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; Main task ; Compilation ;
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; Revision Name ; spw_fifo_ulight ;
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; Revision Name ; spw_fifo_ulight ;
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+-------------------+---------------------+
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+-------------------+---------------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Flow Non-Default Global Settings ;
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; Flow Non-Default Global Settings ;
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+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------+
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+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------+
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; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
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; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
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+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------+
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+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------+
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; ALLOW_REGISTER_DUPLICATION ; Off ; On ; -- ; -- ;
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; ALLOW_REGISTER_DUPLICATION ; Off ; On ; -- ; -- ;
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; ALLOW_REGISTER_MERGING ; Off ; On ; -- ; -- ;
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; ALLOW_REGISTER_MERGING ; Off ; On ; -- ; -- ;
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; ALLOW_REGISTER_RETIMING ; Off ; On ; -- ; -- ;
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; ALLOW_REGISTER_RETIMING ; Off ; On ; -- ; -- ;
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; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Off ; Auto ; -- ; -- ;
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; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Off ; Auto ; -- ; -- ;
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; ALLOW_SYNCH_CTRL_USAGE ; Off ; On ; -- ; -- ;
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; ALLOW_SYNCH_CTRL_USAGE ; Off ; On ; -- ; -- ;
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; AUTO_DELAY_CHAINS ; Off ; On ; -- ; -- ;
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; AUTO_DELAY_CHAINS ; Off ; On ; -- ; -- ;
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; COMPILER_SIGNATURE_ID ; 31032335263289.150362476611918 ; -- ; -- ; -- ;
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; COMPILER_SIGNATURE_ID ; 31032335263289.150547366508423 ; -- ; -- ; -- ;
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; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
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; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
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; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ;
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; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ;
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; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
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; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/system.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/system.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_defines.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_defines.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/emif.pre.xml ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/emif.pre.xml ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/hps.pre.xml ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/hps.pre.xml ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_PARTITION ; On ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_PARTITION ; On ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; INFER_RAMS_FROM_RAW_LOGIC ; Off ; On ; -- ; -- ;
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; INFER_RAMS_FROM_RAW_LOGIC ; Off ; On ; -- ; -- ;
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; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
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; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
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; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
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; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/../ulight_fifo.cmp ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/../ulight_fifo.cmp ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/ulight_fifo_hps_0_hps.svd ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/ulight_fifo_hps_0_hps.svd ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/../../ulight_fifo.qsys ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/../../ulight_fifo.qsys ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/system.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/system.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.c ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.c ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.c ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.c ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/tclrpt.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_defines.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_defines.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/emif.pre.xml ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/emif.pre.xml ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/hps.pre.xml ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/hps.pre.xml ; -- ; -- ; -- ;
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; OPTIMIZATION_TECHNIQUE ; Speed ; Balanced ; -- ; -- ;
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; OPTIMIZATION_TECHNIQUE ; Speed ; Balanced ; -- ; -- ;
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; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Off ; Normal ; -- ; -- ;
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; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Off ; Normal ; -- ; -- ;
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; OPTIMIZE_POWER_DURING_FITTING ; Extra effort ; Normal compilation ; -- ; -- ;
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; OPTIMIZE_POWER_DURING_FITTING ; Extra effort ; Normal compilation ; -- ; -- ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
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; PHYSICAL_SYNTHESIS_EFFORT ; Extra ; Normal ; -- ; -- ;
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; PHYSICAL_SYNTHESIS_EFFORT ; Extra ; Normal ; -- ; -- ;
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; PLACEMENT_EFFORT_MULTIPLIER ; 40.0 ; 1.0 ; -- ; -- ;
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; PLACEMENT_EFFORT_MULTIPLIER ; 90.0 ; 1.0 ; -- ; -- ;
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; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
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; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
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; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
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; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
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; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
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; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
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; REMOVE_DUPLICATE_REGISTERS ; Off ; On ; -- ; -- ;
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; REMOVE_DUPLICATE_REGISTERS ; Off ; On ; -- ; -- ;
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; ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ; Off ; Auto ; -- ; -- ;
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; ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ; Off ; Auto ; -- ; -- ;
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; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ;
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; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ;
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; ROUTER_TIMING_OPTIMIZATION_LEVEL ; MAXIMUM ; Normal ; -- ; -- ;
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; ROUTER_TIMING_OPTIMIZATION_LEVEL ; MAXIMUM ; Normal ; -- ; -- ;
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; SEED ; 893763639 ; 1 ; -- ; -- ;
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; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.regmap ; -- ; -- ; -- ;
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; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.regmap ; -- ; -- ; -- ;
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; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.debuginfo ; -- ; -- ; -- ;
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; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.debuginfo ; -- ; -- ; -- ;
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; SLD_INFO ; QSYS_NAME ulight_fifo HAS_SOPCINFO 1 GENERATION_ID 1502975928 ; -- ; ulight_fifo ; -- ;
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; SLD_INFO ; QSYS_NAME ulight_fifo HAS_SOPCINFO 1 GENERATION_ID 1502975928 ; -- ; ulight_fifo ; -- ;
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; SOPCINFO_FILE ; ulight_fifo/synthesis/../../ulight_fifo.sopcinfo ; -- ; -- ; -- ;
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; SOPCINFO_FILE ; ulight_fifo/synthesis/../../ulight_fifo.sopcinfo ; -- ; -- ; -- ;
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; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ;
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; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ;
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; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ;
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; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ;
|
; TOP_LEVEL_ENTITY ; SPW_ULIGHT_FIFO ; spw_fifo_ulight ; -- ; -- ;
|
; TOP_LEVEL_ENTITY ; SPW_ULIGHT_FIFO ; spw_fifo_ulight ; -- ; -- ;
|
+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------+
|
+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------+
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------+
|
+-------------------------------------------------------------------------------------------------------------------------------+
|
; Flow Elapsed Time ;
|
; Flow Elapsed Time ;
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
; Analysis & Synthesis ; 00:01:13 ; 1.3 ; 1332 MB ; 00:01:47 ;
|
; Analysis & Synthesis ; 00:01:16 ; 1.3 ; 1339 MB ; 00:01:53 ;
|
; Fitter ; 00:03:16 ; 1.0 ; 2094 MB ; 00:05:44 ;
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; Fitter ; 00:04:42 ; 1.0 ; 2064 MB ; 00:08:17 ;
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; Assembler ; 00:00:16 ; 1.0 ; 1026 MB ; 00:00:10 ;
|
; Assembler ; 00:00:18 ; 1.0 ; 1040 MB ; 00:00:12 ;
|
; TimeQuest Timing Analyzer ; 00:00:40 ; 1.5 ; 1351 MB ; 00:00:57 ;
|
; TimeQuest Timing Analyzer ; 00:00:54 ; 1.5 ; 1351 MB ; 00:01:15 ;
|
; EDA Netlist Writer ; 00:00:07 ; 1.0 ; 1296 MB ; 00:00:07 ;
|
; EDA Netlist Writer ; 00:00:08 ; 1.0 ; 1314 MB ; 00:00:08 ;
|
; Total ; 00:05:32 ; -- ; -- ; 00:08:45 ;
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; Total ; 00:07:18 ; -- ; -- ; 00:11:45 ;
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
|
|
|
|
|
+-----------------------------------------------------------------------------------------+
|
+-----------------------------------------------------------------------------------------+
|
; Flow OS Summary ;
|
; Flow OS Summary ;
|
+---------------------------+------------------+------------+------------+----------------+
|
+---------------------------+------------------+------------+------------+----------------+
|
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
|
+---------------------------+------------------+------------+------------+----------------+
|
+---------------------------+------------------+------------+------------+----------------+
|
; Analysis & Synthesis ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;
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; Analysis & Synthesis ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;
|
; Fitter ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;
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; Fitter ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;
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; Assembler ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;
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; Assembler ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;
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; TimeQuest Timing Analyzer ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;
|
; TimeQuest Timing Analyzer ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;
|
; EDA Netlist Writer ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;
|
; EDA Netlist Writer ; linux-hjij.suse ; SUSE LINUX ; 42 ; x86_64 ;
|
+---------------------------+------------------+------------+------------+----------------+
|
+---------------------------+------------------+------------+------------+----------------+
|
|
|
|
|
------------
|
------------
|
; Flow Log ;
|
; Flow Log ;
|
------------
|
------------
|
quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight
|
quartus_map --read_settings_files=on --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight
|
quartus_fit --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight
|
quartus_fit --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight
|
quartus_asm --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight
|
quartus_asm --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight
|
quartus_sta spw_fifo_ulight -c spw_fifo_ulight
|
quartus_sta spw_fifo_ulight -c spw_fifo_ulight
|
quartus_eda --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight
|
quartus_eda --read_settings_files=off --write_settings_files=off spw_fifo_ulight -c spw_fifo_ulight
|
|
|
|
|
|
|
|
|
