// (C) 2001-2017 Intel Corporation. All rights reserved.
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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// agreement for further details.
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`timescale 1 ps / 1 ps
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`timescale 1 ps / 1 ps
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module hps_sdram_p0_acv_hard_addr_cmd_pads(
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module hps_sdram_p0_acv_hard_addr_cmd_pads(
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/*
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/*
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config_data_in,
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config_data_in,
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config_clock_in,
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config_clock_in,
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config_io_ena,
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config_io_ena,
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config_update,
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config_update,
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*/
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*/
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reset_n,
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reset_n,
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reset_n_afi_clk,
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reset_n_afi_clk,
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pll_hr_clk,
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pll_hr_clk,
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pll_avl_phy_clk,
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pll_avl_phy_clk,
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pll_afi_clk,
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pll_afi_clk,
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pll_mem_clk,
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pll_mem_clk,
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pll_write_clk,
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pll_write_clk,
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phy_ddio_address,
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phy_ddio_address,
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dll_delayctrl_in,
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dll_delayctrl_in,
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phy_ddio_bank,
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phy_ddio_bank,
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phy_ddio_cs_n,
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phy_ddio_cs_n,
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phy_ddio_cke,
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phy_ddio_cke,
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phy_ddio_odt,
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phy_ddio_odt,
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phy_ddio_we_n,
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phy_ddio_we_n,
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phy_ddio_ras_n,
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phy_ddio_ras_n,
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phy_ddio_cas_n,
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phy_ddio_cas_n,
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phy_ddio_ck,
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phy_ddio_ck,
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phy_ddio_reset_n,
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phy_ddio_reset_n,
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phy_mem_address,
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phy_mem_address,
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phy_mem_bank,
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phy_mem_bank,
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phy_mem_cs_n,
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phy_mem_cs_n,
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phy_mem_cke,
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phy_mem_cke,
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phy_mem_odt,
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phy_mem_odt,
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phy_mem_we_n,
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phy_mem_we_n,
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phy_mem_ras_n,
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phy_mem_ras_n,
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phy_mem_cas_n,
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phy_mem_cas_n,
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phy_mem_reset_n,
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phy_mem_reset_n,
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phy_mem_ck,
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phy_mem_ck,
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phy_mem_ck_n
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phy_mem_ck_n
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);
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);
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parameter DEVICE_FAMILY = "";
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parameter DEVICE_FAMILY = "";
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parameter MEM_ADDRESS_WIDTH = "";
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parameter MEM_ADDRESS_WIDTH = "";
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parameter MEM_BANK_WIDTH = "";
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parameter MEM_BANK_WIDTH = "";
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parameter MEM_CHIP_SELECT_WIDTH = "";
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parameter MEM_CHIP_SELECT_WIDTH = "";
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parameter MEM_CLK_EN_WIDTH = "";
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parameter MEM_CLK_EN_WIDTH = "";
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parameter MEM_CK_WIDTH = "";
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parameter MEM_CK_WIDTH = "";
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parameter MEM_ODT_WIDTH = "";
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parameter MEM_ODT_WIDTH = "";
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parameter MEM_CONTROL_WIDTH = "";
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parameter MEM_CONTROL_WIDTH = "";
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parameter AFI_ADDRESS_WIDTH = "";
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parameter AFI_ADDRESS_WIDTH = "";
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parameter AFI_BANK_WIDTH = "";
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parameter AFI_BANK_WIDTH = "";
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parameter AFI_CHIP_SELECT_WIDTH = "";
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parameter AFI_CHIP_SELECT_WIDTH = "";
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parameter AFI_CLK_EN_WIDTH = "";
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parameter AFI_CLK_EN_WIDTH = "";
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parameter AFI_ODT_WIDTH = "";
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parameter AFI_ODT_WIDTH = "";
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parameter AFI_CONTROL_WIDTH = "";
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parameter AFI_CONTROL_WIDTH = "";
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parameter DLL_WIDTH = "";
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parameter DLL_WIDTH = "";
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parameter ADC_PHASE_SETTING = "";
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parameter ADC_PHASE_SETTING = "";
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parameter ADC_INVERT_PHASE = "";
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parameter ADC_INVERT_PHASE = "";
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parameter IS_HHP_HPS = "";
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parameter IS_HHP_HPS = "";
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/*
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/*
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input config_data_in;
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input config_data_in;
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input config_clock_in;
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input config_clock_in;
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input config_io_ena;
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input config_io_ena;
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input config_update;
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input config_update;
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*/
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*/
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input reset_n;
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input reset_n;
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input reset_n_afi_clk;
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input reset_n_afi_clk;
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input pll_afi_clk;
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input pll_afi_clk;
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input pll_hr_clk;
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input pll_hr_clk;
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input pll_avl_phy_clk;
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input pll_avl_phy_clk;
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input pll_mem_clk;
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input pll_mem_clk;
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input pll_write_clk;
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input pll_write_clk;
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input [DLL_WIDTH-1:0] dll_delayctrl_in;
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input [DLL_WIDTH-1:0] dll_delayctrl_in;
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input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
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input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
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input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
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input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
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input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
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input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
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input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
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input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
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input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
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input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
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output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
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output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
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output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
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output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
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output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
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output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
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output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
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output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
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output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
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output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
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output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
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output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
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output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
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output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
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output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
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output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
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output phy_mem_reset_n;
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output phy_mem_reset_n;
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output [MEM_CK_WIDTH-1:0] phy_mem_ck;
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output [MEM_CK_WIDTH-1:0] phy_mem_ck;
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output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
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output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
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/* ********* *
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/* ********* *
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* A/C Logic *
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* A/C Logic *
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* ********* */
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* ********* */
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localparam CMD_WIDTH =
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localparam CMD_WIDTH =
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MEM_CHIP_SELECT_WIDTH +
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MEM_CHIP_SELECT_WIDTH +
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MEM_CLK_EN_WIDTH +
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MEM_CLK_EN_WIDTH +
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MEM_ODT_WIDTH +
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MEM_ODT_WIDTH +
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MEM_CONTROL_WIDTH +
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MEM_CONTROL_WIDTH +
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MEM_CONTROL_WIDTH +
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MEM_CONTROL_WIDTH +
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MEM_CONTROL_WIDTH;
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MEM_CONTROL_WIDTH;
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localparam AC_CLK_WIDTH = MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH + 1;
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localparam AC_CLK_WIDTH = MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH + 1;
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localparam IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC = "false";
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localparam IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC = "false";
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wire [AC_CLK_WIDTH-1:0] ac_clk;
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wire [AC_CLK_WIDTH-1:0] ac_clk;
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generate
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generate
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genvar i;
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genvar i;
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for (i = 0; i < AC_CLK_WIDTH; i = i + 1)
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for (i = 0; i < AC_CLK_WIDTH; i = i + 1)
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begin: address_gen
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begin: address_gen
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wire addr_cmd_clk;
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wire addr_cmd_clk;
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hps_sdram_p0_acv_ldc # (
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hps_sdram_p0_acv_ldc # (
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.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
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.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
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.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
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.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
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.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
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.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
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.IS_HHP_HPS(IS_HHP_HPS)
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.IS_HHP_HPS(IS_HHP_HPS)
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) acv_ac_ldc (
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) acv_ac_ldc (
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.pll_hr_clk(pll_avl_phy_clk),
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.pll_hr_clk(pll_avl_phy_clk),
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.pll_dq_clk(pll_write_clk),
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.pll_dq_clk(pll_write_clk),
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.pll_dqs_clk (pll_mem_clk),
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.pll_dqs_clk (pll_mem_clk),
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.dll_phy_delayctrl(dll_delayctrl_in),
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.dll_phy_delayctrl(dll_delayctrl_in),
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.adc_clk_cps(ac_clk[i])
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.adc_clk_cps(ac_clk[i])
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);
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);
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end
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end
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endgenerate
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endgenerate
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hps_sdram_p0_generic_ddio uaddress_pad(
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hps_sdram_p0_generic_ddio uaddress_pad(
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.datain(phy_ddio_address),
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.datain(phy_ddio_address),
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.halfratebypass(1'b1),
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.halfratebypass(1'b1),
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.dataout(phy_mem_address),
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.dataout(phy_mem_address),
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.clk_hr({MEM_ADDRESS_WIDTH{pll_hr_clk}}),
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.clk_hr({MEM_ADDRESS_WIDTH{pll_hr_clk}}),
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.clk_fr(ac_clk[MEM_ADDRESS_WIDTH-1:0])
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.clk_fr(ac_clk[MEM_ADDRESS_WIDTH-1:0])
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);
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);
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defparam uaddress_pad.WIDTH = MEM_ADDRESS_WIDTH;
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defparam uaddress_pad.WIDTH = MEM_ADDRESS_WIDTH;
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hps_sdram_p0_generic_ddio ubank_pad(
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hps_sdram_p0_generic_ddio ubank_pad(
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.datain(phy_ddio_bank),
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.datain(phy_ddio_bank),
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.halfratebypass(1'b1),
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.halfratebypass(1'b1),
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.dataout(phy_mem_bank),
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.dataout(phy_mem_bank),
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.clk_hr({MEM_BANK_WIDTH{pll_hr_clk}}),
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.clk_hr({MEM_BANK_WIDTH{pll_hr_clk}}),
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.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH - 1: MEM_ADDRESS_WIDTH])
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.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH - 1: MEM_ADDRESS_WIDTH])
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);
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);
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defparam ubank_pad.WIDTH = MEM_BANK_WIDTH;
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defparam ubank_pad.WIDTH = MEM_BANK_WIDTH;
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hps_sdram_p0_generic_ddio ucmd_pad(
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hps_sdram_p0_generic_ddio ucmd_pad(
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.datain({
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.datain({
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phy_ddio_we_n,
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phy_ddio_we_n,
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phy_ddio_cas_n,
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phy_ddio_cas_n,
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phy_ddio_ras_n,
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phy_ddio_ras_n,
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phy_ddio_odt,
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phy_ddio_odt,
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phy_ddio_cke,
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phy_ddio_cke,
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phy_ddio_cs_n
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phy_ddio_cs_n
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}),
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}),
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.halfratebypass(1'b1),
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.halfratebypass(1'b1),
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.dataout({
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.dataout({
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phy_mem_we_n,
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phy_mem_we_n,
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phy_mem_cas_n,
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phy_mem_cas_n,
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phy_mem_ras_n,
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phy_mem_ras_n,
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phy_mem_odt,
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phy_mem_odt,
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phy_mem_cke,
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phy_mem_cke,
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phy_mem_cs_n
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phy_mem_cs_n
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}),
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}),
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.clk_hr({CMD_WIDTH{pll_hr_clk}}),
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.clk_hr({CMD_WIDTH{pll_hr_clk}}),
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.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH - 1: MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH])
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.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH - 1: MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH])
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);
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);
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defparam ucmd_pad.WIDTH = CMD_WIDTH;
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defparam ucmd_pad.WIDTH = CMD_WIDTH;
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hps_sdram_p0_generic_ddio ureset_n_pad(
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hps_sdram_p0_generic_ddio ureset_n_pad(
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.datain(phy_ddio_reset_n),
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.datain(phy_ddio_reset_n),
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.halfratebypass(1'b1),
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.halfratebypass(1'b1),
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.dataout(phy_mem_reset_n),
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.dataout(phy_mem_reset_n),
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.clk_hr(pll_hr_clk),
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.clk_hr(pll_hr_clk),
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.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH])
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.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH])
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);
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);
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defparam ureset_n_pad.WIDTH = 1;
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defparam ureset_n_pad.WIDTH = 1;
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/* ************ *
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/* ************ *
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* Config Logic *
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* Config Logic *
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* ************ */
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* ************ */
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wire [4:0] outputdelaysetting;
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wire [4:0] outputdelaysetting;
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wire [4:0] outputenabledelaysetting;
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wire [4:0] outputenabledelaysetting;
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wire outputhalfratebypass;
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wire outputhalfratebypass;
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wire [4:0] inputdelaysetting;
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wire [4:0] inputdelaysetting;
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wire [1:0] rfifo_clock_select;
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wire [1:0] rfifo_clock_select;
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wire [2:0] rfifo_mode;
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wire [2:0] rfifo_mode;
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/*
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/*
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cyclonev_io_config ioconfig (
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cyclonev_io_config ioconfig (
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.datain(config_data_in),
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.datain(config_data_in),
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.clk(config_clock_in),
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.clk(config_clock_in),
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.ena(config_io_ena),
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.ena(config_io_ena),
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.update(config_update),
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.update(config_update),
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.outputregdelaysetting(outputdelaysetting),
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.outputregdelaysetting(outputdelaysetting),
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.outputenabledelaysetting(outputenabledelaysetting),
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.outputenabledelaysetting(outputenabledelaysetting),
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.outputhalfratebypass(outputhalfratebypass),
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.outputhalfratebypass(outputhalfratebypass),
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.readfiforeadclockselect(rfifo_clock_select),
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.readfiforeadclockselect(rfifo_clock_select),
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.readfifomode(rfifo_mode),
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.readfifomode(rfifo_mode),
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.padtoinputregisterdelaysetting(inputdelaysetting),
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.padtoinputregisterdelaysetting(inputdelaysetting),
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.dataout()
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.dataout()
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);
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);
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*/
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*/
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/* *************** *
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/* *************** *
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* Mem Clock Logic *
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* Mem Clock Logic *
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* *************** */
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* *************** */
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wire [MEM_CK_WIDTH-1:0] mem_ck_source;
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wire [MEM_CK_WIDTH-1:0] mem_ck_source;
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wire [MEM_CK_WIDTH-1:0] mem_ck;
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wire [MEM_CK_WIDTH-1:0] mem_ck;
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generate
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generate
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genvar clock_width;
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genvar clock_width;
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for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
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for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
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begin: clock_gen
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begin: clock_gen
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if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
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if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
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begin
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begin
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hps_sdram_p0_acv_ldc # (
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hps_sdram_p0_acv_ldc # (
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.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
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.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
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.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
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.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
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.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
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.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
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.IS_HHP_HPS(IS_HHP_HPS)
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.IS_HHP_HPS(IS_HHP_HPS)
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) acv_ck_ldc (
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) acv_ck_ldc (
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.pll_hr_clk(pll_avl_phy_clk),
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.pll_hr_clk(pll_avl_phy_clk),
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.pll_dq_clk(pll_write_clk),
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.pll_dq_clk(pll_write_clk),
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.pll_dqs_clk (pll_mem_clk),
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.pll_dqs_clk (pll_mem_clk),
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.dll_phy_delayctrl(dll_delayctrl_in),
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.dll_phy_delayctrl(dll_delayctrl_in),
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.adc_clk_cps(mem_ck_source[clock_width])
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.adc_clk_cps(mem_ck_source[clock_width])
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);
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);
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end
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end
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else
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else
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begin
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begin
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wire [3:0] phy_clk_in;
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wire [3:0] phy_clk_in;
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wire [3:0] phy_clk_out;
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wire [3:0] phy_clk_out;
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assign phy_clk_in = {pll_avl_phy_clk,pll_write_clk,pll_mem_clk,1'b0};
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assign phy_clk_in = {pll_avl_phy_clk,pll_write_clk,pll_mem_clk,1'b0};
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|
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if (IS_HHP_HPS == "true") begin
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if (IS_HHP_HPS == "true") begin
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assign phy_clk_out = phy_clk_in;
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assign phy_clk_out = phy_clk_in;
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end else begin
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end else begin
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cyclonev_phy_clkbuf phy_clkbuf (
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cyclonev_phy_clkbuf phy_clkbuf (
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.inclk (phy_clk_in),
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.inclk (phy_clk_in),
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.outclk (phy_clk_out)
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.outclk (phy_clk_out)
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);
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);
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end
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end
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|
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wire [3:0] leveled_dqs_clocks;
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wire [3:0] leveled_dqs_clocks;
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cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
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cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
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.clkin (phy_clk_out[1]),
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.clkin (phy_clk_out[1]),
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.delayctrlin (dll_delayctrl_in),
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.delayctrlin (dll_delayctrl_in),
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.clkout(leveled_dqs_clocks)
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.clkout(leveled_dqs_clocks)
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);
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);
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defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
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defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
|
|
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cyclonev_clk_phase_select clk_phase_select_dqs (
|
cyclonev_clk_phase_select clk_phase_select_dqs (
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`ifndef SIMGEN
|
`ifndef SIMGEN
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.clkin (leveled_dqs_clocks[0]),
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.clkin (leveled_dqs_clocks[0]),
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`else
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`else
|
.clkin (leveled_dqs_clocks),
|
.clkin (leveled_dqs_clocks),
|
`endif
|
`endif
|
.clkout (mem_ck_source[clock_width])
|
.clkout (mem_ck_source[clock_width])
|
);
|
);
|
defparam clk_phase_select_dqs.physical_clock_source = "DQS";
|
defparam clk_phase_select_dqs.physical_clock_source = "DQS";
|
defparam clk_phase_select_dqs.use_phasectrlin = "false";
|
defparam clk_phase_select_dqs.use_phasectrlin = "false";
|
defparam clk_phase_select_dqs.phase_setting = 0;
|
defparam clk_phase_select_dqs.phase_setting = 0;
|
end
|
end
|
|
|
wire mem_ck_hi;
|
wire mem_ck_hi;
|
wire mem_ck_lo;
|
wire mem_ck_lo;
|
|
|
if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
|
if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
|
begin
|
begin
|
assign mem_ck_hi = 1'b0;
|
assign mem_ck_hi = 1'b0;
|
assign mem_ck_lo = 1'b1;
|
assign mem_ck_lo = 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
assign mem_ck_hi = phy_ddio_ck[0];
|
assign mem_ck_hi = phy_ddio_ck[0];
|
assign mem_ck_lo = phy_ddio_ck[1];
|
assign mem_ck_lo = phy_ddio_ck[1];
|
end
|
end
|
|
|
altddio_out umem_ck_pad(
|
altddio_out umem_ck_pad(
|
.aclr (1'b0),
|
.aclr (1'b0),
|
.aset (1'b0),
|
.aset (1'b0),
|
.datain_h (mem_ck_hi),
|
.datain_h (mem_ck_hi),
|
.datain_l (mem_ck_lo),
|
.datain_l (mem_ck_lo),
|
.dataout (mem_ck[clock_width]),
|
.dataout (mem_ck[clock_width]),
|
.oe (1'b1),
|
.oe (1'b1),
|
.outclock (mem_ck_source[clock_width]),
|
.outclock (mem_ck_source[clock_width]),
|
.outclocken (1'b1)
|
.outclocken (1'b1)
|
);
|
);
|
|
|
defparam
|
defparam
|
umem_ck_pad.extend_oe_disable = "UNUSED",
|
umem_ck_pad.extend_oe_disable = "UNUSED",
|
umem_ck_pad.intended_device_family = DEVICE_FAMILY,
|
umem_ck_pad.intended_device_family = DEVICE_FAMILY,
|
umem_ck_pad.invert_output = "OFF",
|
umem_ck_pad.invert_output = "OFF",
|
umem_ck_pad.lpm_hint = "UNUSED",
|
umem_ck_pad.lpm_hint = "UNUSED",
|
umem_ck_pad.lpm_type = "altddio_out",
|
umem_ck_pad.lpm_type = "altddio_out",
|
umem_ck_pad.oe_reg = "UNUSED",
|
umem_ck_pad.oe_reg = "UNUSED",
|
umem_ck_pad.power_up_high = "OFF",
|
umem_ck_pad.power_up_high = "OFF",
|
umem_ck_pad.width = 1;
|
umem_ck_pad.width = 1;
|
|
|
wire mem_ck_temp;
|
wire mem_ck_temp;
|
|
|
assign mem_ck_temp = mem_ck[clock_width];
|
assign mem_ck_temp = mem_ck[clock_width];
|
|
|
hps_sdram_p0_clock_pair_generator uclk_generator(
|
hps_sdram_p0_clock_pair_generator uclk_generator(
|
.datain (mem_ck_temp),
|
.datain (mem_ck_temp),
|
.dataout (phy_mem_ck[clock_width]),
|
.dataout (phy_mem_ck[clock_width]),
|
.dataout_b (phy_mem_ck_n[clock_width])
|
.dataout_b (phy_mem_ck_n[clock_width])
|
);
|
);
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
|
|
endmodule
|
endmodule
|
|
|
