// (C) 2001-2017 Intel Corporation. All rights reserved.
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// (C) 2001-2017 Intel Corporation. All rights reserved.
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// Your use of Intel Corporation's design tools, logic functions and other
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// Your use of Intel Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files from any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License Subscription
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// to the terms and conditions of the Intel Program License Subscription
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// Agreement, Intel MegaCore Function License Agreement, or other applicable
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// Agreement, Intel FPGA IP License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// sole purpose of programming logic devices manufactured by Intel and sold by
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// Intel or its authorized distributors. Please refer to the applicable
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// Intel or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// agreement for further details.
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`timescale 1 ps / 1 ps
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`timescale 1 ps / 1 ps
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module hps_sdram_p0_acv_hard_io_pads(
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module hps_sdram_p0_acv_hard_io_pads(
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reset_n_addr_cmd_clk,
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reset_n_addr_cmd_clk,
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reset_n_afi_clk,
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reset_n_afi_clk,
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oct_ctl_rs_value,
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oct_ctl_rs_value,
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oct_ctl_rt_value,
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oct_ctl_rt_value,
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phy_ddio_address,
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phy_ddio_address,
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phy_ddio_bank,
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phy_ddio_bank,
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phy_ddio_cs_n,
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phy_ddio_cs_n,
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phy_ddio_cke,
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phy_ddio_cke,
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phy_ddio_odt,
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phy_ddio_odt,
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phy_ddio_we_n,
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phy_ddio_we_n,
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phy_ddio_ras_n,
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phy_ddio_ras_n,
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phy_ddio_cas_n,
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phy_ddio_cas_n,
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phy_ddio_ck,
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phy_ddio_ck,
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phy_ddio_reset_n,
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phy_ddio_reset_n,
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phy_mem_address,
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phy_mem_address,
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phy_mem_bank,
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phy_mem_bank,
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phy_mem_cs_n,
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phy_mem_cs_n,
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phy_mem_cke,
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phy_mem_cke,
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phy_mem_odt,
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phy_mem_odt,
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phy_mem_we_n,
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phy_mem_we_n,
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phy_mem_ras_n,
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phy_mem_ras_n,
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phy_mem_cas_n,
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phy_mem_cas_n,
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phy_mem_reset_n,
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phy_mem_reset_n,
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pll_afi_clk,
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pll_afi_clk,
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pll_afi_phy_clk,
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pll_afi_phy_clk,
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pll_avl_phy_clk,
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pll_avl_phy_clk,
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pll_avl_clk,
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pll_avl_clk,
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avl_clk,
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avl_clk,
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pll_mem_clk,
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pll_mem_clk,
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pll_mem_phy_clk,
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pll_mem_phy_clk,
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pll_write_clk,
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pll_write_clk,
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pll_dqs_ena_clk,
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pll_dqs_ena_clk,
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pll_addr_cmd_clk,
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pll_addr_cmd_clk,
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phy_mem_dq,
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phy_mem_dq,
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phy_mem_dm,
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phy_mem_dm,
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phy_mem_ck,
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phy_mem_ck,
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phy_mem_ck_n,
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phy_mem_ck_n,
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mem_dqs,
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mem_dqs,
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mem_dqs_n,
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mem_dqs_n,
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dll_phy_delayctrl,
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dll_phy_delayctrl,
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scc_clk,
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scc_clk,
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scc_data,
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scc_data,
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scc_dqs_ena,
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scc_dqs_ena,
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scc_dqs_io_ena,
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scc_dqs_io_ena,
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scc_dq_ena,
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scc_dq_ena,
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scc_dm_ena,
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scc_dm_ena,
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scc_upd,
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scc_upd,
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seq_read_latency_counter,
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seq_read_latency_counter,
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seq_read_increment_vfifo_fr,
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seq_read_increment_vfifo_fr,
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seq_read_increment_vfifo_hr,
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seq_read_increment_vfifo_hr,
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phy_ddio_dmdout,
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phy_ddio_dmdout,
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phy_ddio_dqdout,
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phy_ddio_dqdout,
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phy_ddio_dqs_oe,
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phy_ddio_dqs_oe,
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phy_ddio_dqsdout,
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phy_ddio_dqsdout,
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phy_ddio_dqsb_oe,
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phy_ddio_dqsb_oe,
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phy_ddio_dqslogic_oct,
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phy_ddio_dqslogic_oct,
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phy_ddio_dqslogic_fiforeset,
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phy_ddio_dqslogic_fiforeset,
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phy_ddio_dqslogic_aclr_pstamble,
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phy_ddio_dqslogic_aclr_pstamble,
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phy_ddio_dqslogic_aclr_fifoctrl,
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phy_ddio_dqslogic_aclr_fifoctrl,
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phy_ddio_dqslogic_incwrptr,
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phy_ddio_dqslogic_incwrptr,
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phy_ddio_dqslogic_readlatency,
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phy_ddio_dqslogic_readlatency,
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ddio_phy_dqslogic_rdatavalid,
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ddio_phy_dqslogic_rdatavalid,
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ddio_phy_dqdin,
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ddio_phy_dqdin,
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phy_ddio_dqslogic_incrdataen,
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phy_ddio_dqslogic_incrdataen,
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phy_ddio_dqslogic_dqsena,
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phy_ddio_dqslogic_dqsena,
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phy_ddio_dqoe,
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phy_ddio_dqoe,
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capture_strobe_tracking
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capture_strobe_tracking
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);
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);
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parameter DEVICE_FAMILY = "";
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parameter DEVICE_FAMILY = "";
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parameter FAST_SIM_MODEL = 0;
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parameter FAST_SIM_MODEL = 0;
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parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
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parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
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parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
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parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
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parameter MEM_ADDRESS_WIDTH = "";
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parameter MEM_ADDRESS_WIDTH = "";
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parameter MEM_BANK_WIDTH = "";
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parameter MEM_BANK_WIDTH = "";
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parameter MEM_CHIP_SELECT_WIDTH = "";
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parameter MEM_CHIP_SELECT_WIDTH = "";
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parameter MEM_CLK_EN_WIDTH = "";
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parameter MEM_CLK_EN_WIDTH = "";
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parameter MEM_CK_WIDTH = "";
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parameter MEM_CK_WIDTH = "";
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parameter MEM_ODT_WIDTH = "";
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parameter MEM_ODT_WIDTH = "";
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parameter MEM_DQS_WIDTH = "";
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parameter MEM_DQS_WIDTH = "";
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parameter MEM_DM_WIDTH = "";
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parameter MEM_DM_WIDTH = "";
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parameter MEM_CONTROL_WIDTH = "";
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parameter MEM_CONTROL_WIDTH = "";
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parameter MEM_DQ_WIDTH = "";
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parameter MEM_DQ_WIDTH = "";
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parameter MEM_READ_DQS_WIDTH = "";
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parameter MEM_READ_DQS_WIDTH = "";
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parameter MEM_WRITE_DQS_WIDTH = "";
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parameter MEM_WRITE_DQS_WIDTH = "";
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parameter DLL_DELAY_CTRL_WIDTH = "";
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parameter DLL_DELAY_CTRL_WIDTH = "";
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parameter ADC_PHASE_SETTING = "";
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parameter ADC_PHASE_SETTING = "";
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parameter ADC_INVERT_PHASE = "";
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parameter ADC_INVERT_PHASE = "";
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parameter IS_HHP_HPS = "";
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parameter IS_HHP_HPS = "";
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localparam AFI_ADDRESS_WIDTH = 64;
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localparam AFI_ADDRESS_WIDTH = 64;
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localparam AFI_BANK_WIDTH = 12;
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localparam AFI_BANK_WIDTH = 12;
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localparam AFI_CHIP_SELECT_WIDTH = 8;
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localparam AFI_CHIP_SELECT_WIDTH = 8;
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localparam AFI_CLK_EN_WIDTH = 8;
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localparam AFI_CLK_EN_WIDTH = 8;
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localparam AFI_ODT_WIDTH = 8;
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localparam AFI_ODT_WIDTH = 8;
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localparam AFI_DATA_MASK_WIDTH = 20;
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localparam AFI_DATA_MASK_WIDTH = 20;
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localparam AFI_CONTROL_WIDTH = 4;
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localparam AFI_CONTROL_WIDTH = 4;
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input reset_n_afi_clk;
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input reset_n_afi_clk;
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input reset_n_addr_cmd_clk;
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input reset_n_addr_cmd_clk;
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input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
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input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
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input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
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input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
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input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
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input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
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input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
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input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
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input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
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input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
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input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
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input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
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input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
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input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
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input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
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output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
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output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
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output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
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output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
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output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
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output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
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output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
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output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
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output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
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output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
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output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
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output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
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output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
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output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
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output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
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output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
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output phy_mem_reset_n;
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output phy_mem_reset_n;
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input pll_afi_clk;
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input pll_afi_clk;
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input pll_afi_phy_clk;
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input pll_afi_phy_clk;
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input pll_avl_phy_clk;
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input pll_avl_phy_clk;
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input pll_avl_clk;
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input pll_avl_clk;
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input avl_clk;
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input avl_clk;
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input pll_mem_clk;
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input pll_mem_clk;
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input pll_mem_phy_clk;
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input pll_mem_phy_clk;
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input pll_write_clk;
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input pll_write_clk;
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input pll_dqs_ena_clk;
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input pll_dqs_ena_clk;
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input pll_addr_cmd_clk;
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input pll_addr_cmd_clk;
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inout [MEM_DQ_WIDTH-1:0] phy_mem_dq;
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inout [MEM_DQ_WIDTH-1:0] phy_mem_dq;
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output [MEM_DM_WIDTH-1:0] phy_mem_dm;
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output [MEM_DM_WIDTH-1:0] phy_mem_dm;
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output [MEM_CK_WIDTH-1:0] phy_mem_ck;
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output [MEM_CK_WIDTH-1:0] phy_mem_ck;
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output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
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output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
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inout [MEM_DQS_WIDTH-1:0] mem_dqs;
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inout [MEM_DQS_WIDTH-1:0] mem_dqs;
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inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
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inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
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input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
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input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
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input scc_clk;
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input scc_clk;
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input scc_data;
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input scc_data;
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input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
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input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
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input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
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input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
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input [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
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input [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
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input [MEM_DM_WIDTH - 1:0] scc_dm_ena;
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input [MEM_DM_WIDTH - 1:0] scc_dm_ena;
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input [4:0] seq_read_latency_counter;
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input [4:0] seq_read_latency_counter;
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input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_fr;
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input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_fr;
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input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_hr;
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input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_hr;
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input scc_upd;
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input scc_upd;
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output [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
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output [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
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input [24 : 0] phy_ddio_dmdout;
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input [24 : 0] phy_ddio_dmdout;
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input [179 : 0] phy_ddio_dqdout;
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input [179 : 0] phy_ddio_dqdout;
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input [9 : 0] phy_ddio_dqs_oe;
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input [9 : 0] phy_ddio_dqs_oe;
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input [19 : 0] phy_ddio_dqsdout;
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input [19 : 0] phy_ddio_dqsdout;
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input [9 : 0] phy_ddio_dqsb_oe;
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input [9 : 0] phy_ddio_dqsb_oe;
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input [9 : 0] phy_ddio_dqslogic_oct;
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input [9 : 0] phy_ddio_dqslogic_oct;
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input [4 : 0] phy_ddio_dqslogic_fiforeset;
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input [4 : 0] phy_ddio_dqslogic_fiforeset;
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input [4 : 0] phy_ddio_dqslogic_aclr_pstamble;
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input [4 : 0] phy_ddio_dqslogic_aclr_pstamble;
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input [4 : 0] phy_ddio_dqslogic_aclr_fifoctrl;
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input [4 : 0] phy_ddio_dqslogic_aclr_fifoctrl;
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input [9 : 0] phy_ddio_dqslogic_incwrptr;
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input [9 : 0] phy_ddio_dqslogic_incwrptr;
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input [24 : 0] phy_ddio_dqslogic_readlatency;
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input [24 : 0] phy_ddio_dqslogic_readlatency;
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output [4 : 0] ddio_phy_dqslogic_rdatavalid;
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output [4 : 0] ddio_phy_dqslogic_rdatavalid;
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output [179 : 0] ddio_phy_dqdin;
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output [179 : 0] ddio_phy_dqdin;
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input [9 : 0] phy_ddio_dqslogic_incrdataen;
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input [9 : 0] phy_ddio_dqslogic_incrdataen;
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input [9 : 0] phy_ddio_dqslogic_dqsena;
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input [9 : 0] phy_ddio_dqslogic_dqsena;
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input [89 : 0] phy_ddio_dqoe;
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input [89 : 0] phy_ddio_dqoe;
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wire [MEM_DQ_WIDTH-1:0] mem_phy_dq;
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wire [MEM_DQ_WIDTH-1:0] mem_phy_dq;
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wire [DLL_DELAY_CTRL_WIDTH-1:0] read_bidir_dll_phy_delayctrl;
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wire [DLL_DELAY_CTRL_WIDTH-1:0] read_bidir_dll_phy_delayctrl;
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wire [MEM_READ_DQS_WIDTH-1:0] bidir_read_dqs_bus_out;
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wire [MEM_READ_DQS_WIDTH-1:0] bidir_read_dqs_bus_out;
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wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_high;
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wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_high;
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wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_low;
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wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_low;
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wire dqs_busout;
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wire dqs_busout;
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wire hr_clk = pll_avl_clk;
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wire hr_clk = pll_avl_clk;
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wire core_clk = pll_afi_clk;
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wire core_clk = pll_afi_clk;
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wire reset_n_core_clk = reset_n_afi_clk;
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wire reset_n_core_clk = reset_n_afi_clk;
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hps_sdram_p0_acv_hard_addr_cmd_pads uaddr_cmd_pads(
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hps_sdram_p0_acv_hard_addr_cmd_pads uaddr_cmd_pads(
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/*
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/*
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.config_data_in(config_data_in),
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.config_data_in(config_data_in),
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.config_clock_in(config_clock_in),
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.config_clock_in(config_clock_in),
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.config_io_ena(config_io_ena),
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.config_io_ena(config_io_ena),
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.config_update(config_update),
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.config_update(config_update),
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*/
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*/
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.reset_n (reset_n_addr_cmd_clk),
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.reset_n (reset_n_addr_cmd_clk),
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.reset_n_afi_clk (reset_n_afi_clk),
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.reset_n_afi_clk (reset_n_afi_clk),
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.pll_afi_clk (pll_afi_phy_clk),
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.pll_afi_clk (pll_afi_phy_clk),
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.pll_mem_clk (pll_mem_phy_clk),
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.pll_mem_clk (pll_mem_phy_clk),
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.pll_hr_clk (hr_clk),
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.pll_hr_clk (hr_clk),
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.pll_avl_phy_clk (pll_avl_phy_clk),
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.pll_avl_phy_clk (pll_avl_phy_clk),
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.pll_write_clk (pll_write_clk),
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.pll_write_clk (pll_write_clk),
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.dll_delayctrl_in (dll_phy_delayctrl),
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.dll_delayctrl_in (dll_phy_delayctrl),
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.phy_ddio_address (phy_ddio_address),
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.phy_ddio_address (phy_ddio_address),
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.phy_ddio_bank (phy_ddio_bank),
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.phy_ddio_bank (phy_ddio_bank),
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.phy_ddio_cs_n (phy_ddio_cs_n),
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.phy_ddio_cs_n (phy_ddio_cs_n),
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.phy_ddio_cke (phy_ddio_cke),
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.phy_ddio_cke (phy_ddio_cke),
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.phy_ddio_odt (phy_ddio_odt),
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.phy_ddio_odt (phy_ddio_odt),
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.phy_ddio_we_n (phy_ddio_we_n),
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.phy_ddio_we_n (phy_ddio_we_n),
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.phy_ddio_ras_n (phy_ddio_ras_n),
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.phy_ddio_ras_n (phy_ddio_ras_n),
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.phy_ddio_cas_n (phy_ddio_cas_n),
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.phy_ddio_cas_n (phy_ddio_cas_n),
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.phy_ddio_ck (phy_ddio_ck),
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.phy_ddio_ck (phy_ddio_ck),
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.phy_ddio_reset_n (phy_ddio_reset_n),
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.phy_ddio_reset_n (phy_ddio_reset_n),
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.phy_mem_address (phy_mem_address),
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.phy_mem_address (phy_mem_address),
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.phy_mem_bank (phy_mem_bank),
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.phy_mem_bank (phy_mem_bank),
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.phy_mem_cs_n (phy_mem_cs_n),
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.phy_mem_cs_n (phy_mem_cs_n),
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.phy_mem_cke (phy_mem_cke),
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.phy_mem_cke (phy_mem_cke),
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.phy_mem_odt (phy_mem_odt),
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.phy_mem_odt (phy_mem_odt),
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.phy_mem_we_n (phy_mem_we_n),
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.phy_mem_we_n (phy_mem_we_n),
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.phy_mem_ras_n (phy_mem_ras_n),
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.phy_mem_ras_n (phy_mem_ras_n),
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.phy_mem_cas_n (phy_mem_cas_n),
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.phy_mem_cas_n (phy_mem_cas_n),
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.phy_mem_reset_n (phy_mem_reset_n),
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.phy_mem_reset_n (phy_mem_reset_n),
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.phy_mem_ck (phy_mem_ck),
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.phy_mem_ck (phy_mem_ck),
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.phy_mem_ck_n (phy_mem_ck_n)
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.phy_mem_ck_n (phy_mem_ck_n)
|
);
|
);
|
defparam uaddr_cmd_pads.DEVICE_FAMILY = DEVICE_FAMILY;
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defparam uaddr_cmd_pads.DEVICE_FAMILY = DEVICE_FAMILY;
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defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
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defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
|
defparam uaddr_cmd_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
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defparam uaddr_cmd_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
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defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
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defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
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defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
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defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
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defparam uaddr_cmd_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
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defparam uaddr_cmd_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
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defparam uaddr_cmd_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
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defparam uaddr_cmd_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
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defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
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defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
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defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH * 4;
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defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH * 4;
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defparam uaddr_cmd_pads.AFI_BANK_WIDTH = MEM_BANK_WIDTH * 4;
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defparam uaddr_cmd_pads.AFI_BANK_WIDTH = MEM_BANK_WIDTH * 4;
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defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH * 4;
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defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH * 4;
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defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH * 4;
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defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH * 4;
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defparam uaddr_cmd_pads.AFI_ODT_WIDTH = MEM_ODT_WIDTH * 4;
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defparam uaddr_cmd_pads.AFI_ODT_WIDTH = MEM_ODT_WIDTH * 4;
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defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH = MEM_CONTROL_WIDTH * 4;
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defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH = MEM_CONTROL_WIDTH * 4;
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defparam uaddr_cmd_pads.DLL_WIDTH = DLL_DELAY_CTRL_WIDTH;
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defparam uaddr_cmd_pads.DLL_WIDTH = DLL_DELAY_CTRL_WIDTH;
|
defparam uaddr_cmd_pads.ADC_PHASE_SETTING = ADC_PHASE_SETTING;
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defparam uaddr_cmd_pads.ADC_PHASE_SETTING = ADC_PHASE_SETTING;
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defparam uaddr_cmd_pads.ADC_INVERT_PHASE = ADC_INVERT_PHASE;
|
defparam uaddr_cmd_pads.ADC_INVERT_PHASE = ADC_INVERT_PHASE;
|
defparam uaddr_cmd_pads.IS_HHP_HPS = IS_HHP_HPS;
|
defparam uaddr_cmd_pads.IS_HHP_HPS = IS_HHP_HPS;
|
|
|
localparam NUM_OF_DQDQS = MEM_WRITE_DQS_WIDTH;
|
localparam NUM_OF_DQDQS = MEM_WRITE_DQS_WIDTH;
|
localparam DQDQS_DATA_WIDTH = MEM_DQ_WIDTH / NUM_OF_DQDQS;
|
localparam DQDQS_DATA_WIDTH = MEM_DQ_WIDTH / NUM_OF_DQDQS;
|
|
|
localparam NATIVE_GROUP_SIZE =
|
localparam NATIVE_GROUP_SIZE =
|
(DQDQS_DATA_WIDTH == 8) ? 9 : DQDQS_DATA_WIDTH;
|
(DQDQS_DATA_WIDTH == 8) ? 9 : DQDQS_DATA_WIDTH;
|
|
|
localparam DQDQS_DM_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
|
localparam DQDQS_DM_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
|
|
|
localparam NUM_OF_DQDQS_WITH_DM = MEM_WRITE_DQS_WIDTH;
|
localparam NUM_OF_DQDQS_WITH_DM = MEM_WRITE_DQS_WIDTH;
|
|
|
generate
|
generate
|
genvar i;
|
genvar i;
|
for (i=0; i<NUM_OF_DQDQS; i=i+1)
|
for (i=0; i<NUM_OF_DQDQS; i=i+1)
|
begin: dq_ddio
|
begin: dq_ddio
|
hps_sdram_p0_altdqdqs ubidir_dq_dqs (
|
hps_sdram_p0_altdqdqs ubidir_dq_dqs (
|
.write_strobe_clock_in (pll_mem_phy_clk),
|
.write_strobe_clock_in (pll_mem_phy_clk),
|
.reset_n_core_clock_in (reset_n_core_clk),
|
.reset_n_core_clock_in (reset_n_core_clk),
|
.core_clock_in (core_clk),
|
.core_clock_in (core_clk),
|
.fr_clock_in (pll_write_clk),
|
.fr_clock_in (pll_write_clk),
|
.hr_clock_in (pll_avl_phy_clk),
|
.hr_clock_in (pll_avl_phy_clk),
|
.parallelterminationcontrol_in(oct_ctl_rt_value),
|
.parallelterminationcontrol_in(oct_ctl_rt_value),
|
.seriesterminationcontrol_in(oct_ctl_rs_value),
|
.seriesterminationcontrol_in(oct_ctl_rs_value),
|
.strobe_ena_hr_clock_in (hr_clk),
|
.strobe_ena_hr_clock_in (hr_clk),
|
.capture_strobe_tracking (capture_strobe_tracking[i]),
|
.capture_strobe_tracking (capture_strobe_tracking[i]),
|
.read_write_data_io (phy_mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
|
.read_write_data_io (phy_mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
|
.read_data_out (ddio_phy_dqdin[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*4-1) : (NATIVE_GROUP_SIZE*i*4)]),
|
.read_data_out (ddio_phy_dqdin[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*4-1) : (NATIVE_GROUP_SIZE*i*4)]),
|
.capture_strobe_out(dqs_busout),
|
.capture_strobe_out(dqs_busout),
|
.extra_write_data_in (phy_ddio_dmdout[(i + 1) * 4 - 1 : (i * 4)]),
|
.extra_write_data_in (phy_ddio_dmdout[(i + 1) * 4 - 1 : (i * 4)]),
|
.write_data_in (phy_ddio_dqdout[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*4-1) : (NATIVE_GROUP_SIZE*i*4)]),
|
.write_data_in (phy_ddio_dqdout[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*4-1) : (NATIVE_GROUP_SIZE*i*4)]),
|
.write_oe_in (phy_ddio_dqoe[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*2-1) : (NATIVE_GROUP_SIZE*i*2)]),
|
.write_oe_in (phy_ddio_dqoe[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*2-1) : (NATIVE_GROUP_SIZE*i*2)]),
|
.strobe_io (mem_dqs[i]),
|
.strobe_io (mem_dqs[i]),
|
.strobe_n_io (mem_dqs_n[i]),
|
.strobe_n_io (mem_dqs_n[i]),
|
.output_strobe_ena(phy_ddio_dqs_oe[(i + 1) * 2 - 1 : (i * 2)]),
|
.output_strobe_ena(phy_ddio_dqs_oe[(i + 1) * 2 - 1 : (i * 2)]),
|
.write_strobe(phy_ddio_dqsdout[(i + 1) * 4 - 1 : (i * 4)]),
|
.write_strobe(phy_ddio_dqsdout[(i + 1) * 4 - 1 : (i * 4)]),
|
.oct_ena_in(phy_ddio_dqslogic_oct[(i + 1) * 2 - 1 : (i * 2)]),
|
.oct_ena_in(phy_ddio_dqslogic_oct[(i + 1) * 2 - 1 : (i * 2)]),
|
.extra_write_data_out (phy_mem_dm[i]),
|
.extra_write_data_out (phy_mem_dm[i]),
|
.config_data_in (scc_data),
|
.config_data_in (scc_data),
|
.config_dqs_ena (scc_dqs_ena[i]),
|
.config_dqs_ena (scc_dqs_ena[i]),
|
.config_io_ena (scc_dq_ena[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
|
.config_io_ena (scc_dq_ena[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
|
.config_dqs_io_ena (scc_dqs_io_ena[i]),
|
.config_dqs_io_ena (scc_dqs_io_ena[i]),
|
.config_update (scc_upd),
|
.config_update (scc_upd),
|
.config_clock_in (scc_clk),
|
.config_clock_in (scc_clk),
|
.config_extra_io_ena (scc_dm_ena[i]),
|
.config_extra_io_ena (scc_dm_ena[i]),
|
.lfifo_rdata_en(phy_ddio_dqslogic_incrdataen[(i + 1) * 2 - 1 : (i * 2)]),
|
.lfifo_rdata_en(phy_ddio_dqslogic_incrdataen[(i + 1) * 2 - 1 : (i * 2)]),
|
.lfifo_rdata_en_full(phy_ddio_dqslogic_dqsena[(i + 1) * 2 - 1 : (i * 2)]),
|
.lfifo_rdata_en_full(phy_ddio_dqslogic_dqsena[(i + 1) * 2 - 1 : (i * 2)]),
|
.lfifo_rd_latency(phy_ddio_dqslogic_readlatency[(i + 1) * 5 - 1 : (i * 5)]),
|
.lfifo_rd_latency(phy_ddio_dqslogic_readlatency[(i + 1) * 5 - 1 : (i * 5)]),
|
.lfifo_reset_n (phy_ddio_dqslogic_aclr_fifoctrl[i]),
|
.lfifo_reset_n (phy_ddio_dqslogic_aclr_fifoctrl[i]),
|
.lfifo_rdata_valid(ddio_phy_dqslogic_rdatavalid[i]),
|
.lfifo_rdata_valid(ddio_phy_dqslogic_rdatavalid[i]),
|
.vfifo_qvld(phy_ddio_dqslogic_dqsena[(i + 1) * 2 - 1 : (i * 2)]),
|
.vfifo_qvld(phy_ddio_dqslogic_dqsena[(i + 1) * 2 - 1 : (i * 2)]),
|
.vfifo_inc_wr_ptr(phy_ddio_dqslogic_incwrptr[(i + 1) * 2 - 1 : (i * 2)]),
|
.vfifo_inc_wr_ptr(phy_ddio_dqslogic_incwrptr[(i + 1) * 2 - 1 : (i * 2)]),
|
.vfifo_reset_n (phy_ddio_dqslogic_aclr_pstamble[i]),
|
.vfifo_reset_n (phy_ddio_dqslogic_aclr_pstamble[i]),
|
.dll_delayctrl_in (dll_phy_delayctrl),
|
.dll_delayctrl_in (dll_phy_delayctrl),
|
.rfifo_reset_n(phy_ddio_dqslogic_fiforeset[i])
|
.rfifo_reset_n(phy_ddio_dqslogic_fiforeset[i])
|
);
|
);
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
generate
|
generate
|
genvar j;
|
genvar j;
|
for (j = NUM_OF_DQDQS; j < 5; j=j+1)
|
for (j = NUM_OF_DQDQS; j < 5; j=j+1)
|
begin: to_vcc
|
begin: to_vcc
|
assign ddio_phy_dqslogic_rdatavalid[j] = 1'b1;
|
assign ddio_phy_dqslogic_rdatavalid[j] = 1'b1;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
endmodule
|
endmodule
|
|
|
