# (C) 2001-2017 Intel Corporation. All rights reserved.
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# (C) 2001-2017 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions and other
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# Your use of Intel Corporation's design tools, logic functions and other
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# software and tools, and its AMPP partner logic functions, and any output
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# software and tools, and its AMPP partner logic functions, and any output
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# files any of the foregoing (including device programming or simulation
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# files from any of the foregoing (including device programming or simulation
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# files), and any associated documentation or information are expressly subject
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# files), and any associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License Subscription
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# to the terms and conditions of the Intel Program License Subscription
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# Agreement, Intel MegaCore Function License Agreement, or other applicable
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# Agreement, Intel FPGA IP License Agreement, or other applicable
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# license agreement, including, without limitation, that your use is for the
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# license agreement, including, without limitation, that your use is for the
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# sole purpose of programming logic devices manufactured by Intel and sold by
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# sole purpose of programming logic devices manufactured by Intel and sold by
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# Intel or its authorized distributors. Please refer to the applicable
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# Intel or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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# agreement for further details.
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#####################################################################
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#####################################################################
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#
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#
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# THIS IS AN AUTO-GENERATED FILE!
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# THIS IS AN AUTO-GENERATED FILE!
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# -------------------------------
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# -------------------------------
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# If you modify this files, all your changes will be lost if you
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# If you modify this files, all your changes will be lost if you
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# regenerate the core!
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# regenerate the core!
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#
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#
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# FILE DESCRIPTION
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# FILE DESCRIPTION
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# ----------------
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# ----------------
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# This file specifies the timing properties of the memory device and
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# This file specifies the timing properties of the memory device and
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# of the memory interface
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# of the memory interface
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package require ::quartus::ddr_timing_model
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package require ::quartus::ddr_timing_model
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###################
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###################
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# #
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# #
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# TIMING SETTINGS #
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# TIMING SETTINGS #
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# #
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# #
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###################
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###################
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# Interface Clock Period
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# Interface Clock Period
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set t(CK) 3.333
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set t(CK) 3.333
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# Reference Clock Period
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# Reference Clock Period
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set t(refCK) 8.0
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set t(refCK) 8.0
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# Minimum Clock Period
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# Minimum Clock Period
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set t(min_CK) 2.5
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set t(min_CK) 2.5
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##########################
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##########################
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# Memory timing parameters
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# Memory timing parameters
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##########################
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##########################
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# A/C Setup/Hold
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# A/C Setup/Hold
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set t(IS) 0.35
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set t(IS) 0.35
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set t(IH) 0.35
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set t(IH) 0.35
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# Data Setup/Hold
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# Data Setup/Hold
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set t(DS) 0.225
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set t(DS) 0.225
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set t(DH) 0.225
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set t(DH) 0.225
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# DQS clock edge to DQ data edge (in same group)
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# DQS clock edge to DQ data edge (in same group)
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set t(DQSQ) [expr { 120 / 1000.0 }]
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set t(DQSQ) [expr { 120 / 1000.0 }]
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set t(QH) 0.38
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set t(QH) 0.38
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set t(QH) [expr (0.5*$t(CK)-(0.5-$t(QH))*$t(min_CK))/$t(CK)]
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set t(QH) [expr (0.5*$t(CK)-(0.5-$t(QH))*$t(min_CK))/$t(CK)]
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# Convert QH into time unit so that it's consistent with DQSQ
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# Convert QH into time unit so that it's consistent with DQSQ
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set t(QH_time) [ expr $t(QH) * $t(CK) ]
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set t(QH_time) [ expr $t(QH) * $t(CK) ]
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# DQS to CK input timing
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# DQS to CK input timing
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set t(DSS) 0.2
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set t(DSS) 0.2
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set t(DSH) 0.2
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set t(DSH) 0.2
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set t(DQSS) 0.25
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set t(DQSS) 0.25
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set t(DSS) [expr $t(DSS)*$t(min_CK)/$t(CK)]
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set t(DSS) [expr $t(DSS)*$t(min_CK)/$t(CK)]
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set t(DSH) [expr $t(DSH)*$t(min_CK)/$t(CK)]
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set t(DSH) [expr $t(DSH)*$t(min_CK)/$t(CK)]
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set t(DQSS) [expr 0.5 - $t(DQSS)*$t(min_CK)/$t(CK)]
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set t(DQSS) [expr 0.5 - $t(DQSS)*$t(min_CK)/$t(CK)]
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# DQS Width
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# DQS Width
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set t(QSH) 0.38
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set t(QSH) 0.38
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# Write Levelling parameters
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# Write Levelling parameters
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set t(WLS) [ expr 0.13 * $t(min_CK) ]
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set t(WLS) [ expr 0.13 * $t(min_CK) ]
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set t(WLH) [ expr 0.13 * $t(min_CK) ]
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set t(WLH) [ expr 0.13 * $t(min_CK) ]
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# DQS to CK timing on reads
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# DQS to CK timing on reads
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set t(DQSCK) [expr { 400 / 1000.0 }]
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set t(DQSCK) [expr { 400 / 1000.0 }]
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# FPGA Duty Cycle Distortion
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# FPGA Duty Cycle Distortion
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set t(DCD) 0.0
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set t(DCD) 0.0
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#######################
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#######################
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# Controller parameters
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# Controller parameters
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#######################
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#######################
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set t(RL) 7
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set t(RL) 7
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set t(WL) 6
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set t(WL) 6
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set t(DWIDTH_RATIO) [expr { 1 * 2 }]
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set t(DWIDTH_RATIO) [expr { 1 * 2 }]
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set t(rd_to_wr_turnaround_oct) 2
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set t(rd_to_wr_turnaround_oct) 2
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#####################
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#####################
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# FPGA specifications
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# FPGA specifications
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#####################
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#####################
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# Sequencer VCALIB width. Determins multicycle length
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# Sequencer VCALIB width. Determins multicycle length
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set vcalib_count_width 2
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set vcalib_count_width 2
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set fpga(tPLL_PSERR) 0.0
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set fpga(tPLL_PSERR) 0.0
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set fpga(tPLL_JITTER) 0.0
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set fpga(tPLL_JITTER) 0.0
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# Systematic DCD in the Write Levelling delay chains
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# Systematic DCD in the Write Levelling delay chains
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set t(WL_DCD) [expr [get_micro_node_delay -micro WL_DCD -parameters {IO VPAD} -in_fitter]/1000.0]
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set t(WL_DCD) [expr [get_micro_node_delay -micro WL_DCD -parameters {IO VPAD} -in_fitter]/1000.0]
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# Non-systematic DC jitter in the Write Levelling delay chains
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# Non-systematic DC jitter in the Write Levelling delay chains
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set t(WL_DCJ) [expr [get_micro_node_delay -micro WL_DC_JITTER -parameters {IO VPAD} -in_fitter]/1000.0]
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set t(WL_DCJ) [expr [get_micro_node_delay -micro WL_DC_JITTER -parameters {IO VPAD} -in_fitter]/1000.0]
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# Phase shift error in the Write Levelling delay chains between DQ and DQS
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# Phase shift error in the Write Levelling delay chains between DQ and DQS
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set t(WL_PSE) 0.0
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set t(WL_PSE) 0.0
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# Jitter in the Write Levelling delay chains
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# Jitter in the Write Levelling delay chains
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set t(WL_JITTER) [expr [get_micro_node_delay -micro WL_JITTER -parameters {IO PHY_SHORT} -in_fitter]/1000.0]
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set t(WL_JITTER) [expr [get_micro_node_delay -micro WL_JITTER -parameters {IO PHY_SHORT} -in_fitter]/1000.0]
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set t(WL_JITTER_DIVISION) [expr [get_micro_node_delay -micro WL_JITTER_DIVISION -parameters {IO PHY_SHORT} -in_fitter]/100.0]
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set t(WL_JITTER_DIVISION) [expr [get_micro_node_delay -micro WL_JITTER_DIVISION -parameters {IO PHY_SHORT} -in_fitter]/100.0]
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###############
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###############
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# SSN Info
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# SSN Info
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###############
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###############
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set SSN(pushout_o) [expr [get_micro_node_delay -micro SSO -parameters [list IO DQDQSABSOLUTE NONLEVELED MAX] -in_fitter]/1000.0]
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set SSN(pushout_o) [expr [get_micro_node_delay -micro SSO -parameters [list IO DQDQSABSOLUTE NONLEVELED MAX] -in_fitter]/1000.0]
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set SSN(pullin_o) [expr [get_micro_node_delay -micro SSO -parameters [list IO DQDQSABSOLUTE NONLEVELED MIN] -in_fitter]/-1000.0]
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set SSN(pullin_o) [expr [get_micro_node_delay -micro SSO -parameters [list IO DQDQSABSOLUTE NONLEVELED MIN] -in_fitter]/-1000.0]
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set SSN(pushout_i) [expr [get_micro_node_delay -micro SSI -parameters [list IO DQDQSABSOLUTE NONLEVELED MAX] -in_fitter]/1000.0]
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set SSN(pushout_i) [expr [get_micro_node_delay -micro SSI -parameters [list IO DQDQSABSOLUTE NONLEVELED MAX] -in_fitter]/1000.0]
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set SSN(pullin_i) [expr [get_micro_node_delay -micro SSI -parameters [list IO DQDQSABSOLUTE NONLEVELED MIN] -in_fitter]/-1000.0]
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set SSN(pullin_i) [expr [get_micro_node_delay -micro SSI -parameters [list IO DQDQSABSOLUTE NONLEVELED MIN] -in_fitter]/-1000.0]
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set SSN(rel_pushout_o) [expr [get_micro_node_delay -micro SSO -parameters [list IO DQDQSRELATIVE NONLEVELED MAX] -in_fitter]/1000.0]
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set SSN(rel_pushout_o) [expr [get_micro_node_delay -micro SSO -parameters [list IO DQDQSRELATIVE NONLEVELED MAX] -in_fitter]/1000.0]
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set SSN(rel_pullin_o) [expr [get_micro_node_delay -micro SSO -parameters [list IO DQDQSRELATIVE NONLEVELED MIN] -in_fitter]/-1000.0]
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set SSN(rel_pullin_o) [expr [get_micro_node_delay -micro SSO -parameters [list IO DQDQSRELATIVE NONLEVELED MIN] -in_fitter]/-1000.0]
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set SSN(rel_pushout_i) [expr [get_micro_node_delay -micro SSI -parameters [list IO DQDQSRELATIVE NONLEVELED MAX] -in_fitter]/1000.0]
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set SSN(rel_pushout_i) [expr [get_micro_node_delay -micro SSI -parameters [list IO DQDQSRELATIVE NONLEVELED MAX] -in_fitter]/1000.0]
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set SSN(rel_pullin_i) [expr [get_micro_node_delay -micro SSI -parameters [list IO DQDQSRELATIVE NONLEVELED MIN] -in_fitter]/-1000.0]
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set SSN(rel_pullin_i) [expr [get_micro_node_delay -micro SSI -parameters [list IO DQDQSRELATIVE NONLEVELED MIN] -in_fitter]/-1000.0]
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###############
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###############
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# Board Effects
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# Board Effects
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###############
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###############
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# Intersymbol Interference
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# Intersymbol Interference
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set ISI(addresscmd_setup) 0.0
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set ISI(addresscmd_setup) 0.0
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set ISI(addresscmd_hold) 0.0
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set ISI(addresscmd_hold) 0.0
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set ISI(DQ) 0.0
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set ISI(DQ) 0.0
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set ISI(DQS) 0.0
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set ISI(DQS) 0.0
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set ISI(READ_DQ) 0.0
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set ISI(READ_DQ) 0.0
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set ISI(READ_DQS) 0.0
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set ISI(READ_DQS) 0.0
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# Board skews
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# Board skews
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set board(abs_max_CK_delay) 0.6
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set board(abs_max_CK_delay) 0.6
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set board(abs_max_DQS_delay) 0.6
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set board(abs_max_DQS_delay) 0.6
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set board(minCK_DQS_skew) -0.01
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set board(minCK_DQS_skew) -0.01
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set board(maxCK_DQS_skew) 0.01
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set board(maxCK_DQS_skew) 0.01
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set board(tpd_inter_DIMM) 0.0
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set board(tpd_inter_DIMM) 0.0
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set board(intra_DQS_group_skew) 0.02
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set board(intra_DQS_group_skew) 0.02
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set board(inter_DQS_group_skew) 0.02
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set board(inter_DQS_group_skew) 0.02
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set board(DQ_DQS_skew) 0.0
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set board(DQ_DQS_skew) 0.0
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set board(intra_addr_ctrl_skew) 0.02
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set board(intra_addr_ctrl_skew) 0.02
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set board(addresscmd_CK_skew) 0.0
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set board(addresscmd_CK_skew) 0.0
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