//+FHDR------------------------------------------------------------------------
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//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//FILE NAME :
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//FILE NAME :
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//DEPARTMENT : IC Design / Verification
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//DEPARTMENT : IC Design / Verification
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAMETERS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH [32,16] : width of the data : 32:
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//e.g.DATA_WIDTH [32,16] : width of the data : 32:
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//REUSE ISSUES
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//Reset Strategy :
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//Reset Strategy :
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//Clock Domains :
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//Clock Domains :
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//Critical Timing :
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//Critical Timing :
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//Test Features :
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//Test Features :
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//Asynchronous I/F :
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//Asynchronous I/F :
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//Scan Methodology :
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//Scan Methodology :
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//Instantiations :
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//Instantiations :
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//Synthesizable (y/n) :
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//Synthesizable (y/n) :
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//Other :
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//Other :
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//-FHDR------------------------------------------------------------------------
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//-FHDR------------------------------------------------------------------------
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module FSM_SPW (
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module FSM_SPW (
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input pclk,
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input pclk,
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input resetn,
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input resetn,
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//fsm status control
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//fsm status control
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input auto_start,
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input auto_start,
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input link_start,
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input link_start,
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input link_disable,
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input link_disable,
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//rx status input control
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//rx status input control
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input rx_error,
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input rx_error,
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input rx_credit_error,
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input rx_credit_error,
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input rx_got_bit,
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input rx_got_bit,
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input rx_got_null,
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input rx_got_null,
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input rx_got_nchar,
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input rx_got_nchar,
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input rx_got_time_code,
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input rx_got_time_code,
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input rx_got_fct,
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input rx_got_fct,
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output rx_resetn,
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output rx_resetn,
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//tx status control
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//tx status control
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output enable_tx,
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output enable_tx,
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output send_null_tx,
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output send_null_tx,
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output send_fct_tx,
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output send_fct_tx,
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output [5:0] fsm_state
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output [5:0] fsm_state
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);
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);
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localparam [5:0] error_reset = 6'b00_0000,
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localparam [5:0] error_reset = 6'b00_0000,
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error_wait = 6'b00_0001,
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error_wait = 6'b00_0001,
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ready = 6'b00_0010,
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ready = 6'b00_0010,
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started = 6'b00_0100,
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started = 6'b00_0100,
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connecting = 6'b00_1000,
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connecting = 6'b00_1000,
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run = 6'b01_0000;
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run = 6'b01_0000;
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reg [5:0] state_fsm;
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reg [5:0] state_fsm;
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reg [5:0] next_state_fsm;
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reg [5:0] next_state_fsm;
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reg [11:0] after128us;
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reg [11:0] after128us;
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reg [11:0] after64us;
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reg [11:0] after64us;
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reg [11:0] after850ns;
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reg [11:0] after850ns;
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//
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//
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assign enable_tx = (!resetn | state_fsm == error_reset | state_fsm == error_wait)?1'b0:1'b1;
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assign enable_tx = (!resetn | state_fsm == error_reset | state_fsm == error_wait)?1'b0:1'b1;
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//
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//
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assign rx_resetn = (state_fsm == error_reset)?1'b0:1'b1;
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assign rx_resetn = (state_fsm == error_reset)?1'b0:1'b1;
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//
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//
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assign send_null_tx = (state_fsm == started | state_fsm == connecting | state_fsm == run)?1'b1:1'b0;
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assign send_null_tx = (state_fsm == started | state_fsm == connecting | state_fsm == run)?1'b1:1'b0;
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//
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//
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assign send_fct_tx = (state_fsm == connecting | state_fsm == run)?1'b1:1'b0;
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assign send_fct_tx = (state_fsm == connecting | state_fsm == run)?1'b1:1'b0;
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//
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//
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assign fsm_state = state_fsm;
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assign fsm_state = state_fsm;
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always@(*)
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always@(*)
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begin
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begin
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next_state_fsm = state_fsm;
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next_state_fsm = state_fsm;
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case(state_fsm)
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case(state_fsm)
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error_reset:
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error_reset:
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begin
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begin
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if(after64us == 12'd639)
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if(after64us == 12'd639)
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begin
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begin
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next_state_fsm = error_wait;
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next_state_fsm = error_wait;
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end
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end
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else
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else
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begin
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begin
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next_state_fsm = error_reset;
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next_state_fsm = error_reset;
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end
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end
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end
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end
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error_wait:
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error_wait:
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begin
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begin
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if(after128us == 12'd1279)
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if(after128us == 12'd1279)
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begin
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begin
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next_state_fsm = ready;
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next_state_fsm = ready;
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end
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end
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else if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code)
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else if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code)
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begin
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begin
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next_state_fsm = error_reset;
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next_state_fsm = error_reset;
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end
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end
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end
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end
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ready:
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ready:
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begin
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begin
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if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code)
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if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code)
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begin
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begin
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next_state_fsm = error_reset;
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next_state_fsm = error_reset;
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end
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end
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else if((!link_disable) && (link_start |(auto_start && rx_got_null)))
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else if((!link_disable) && (link_start |(auto_start && rx_got_null)))
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begin
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begin
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next_state_fsm = started;
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next_state_fsm = started;
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end
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end
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end
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end
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started:
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started:
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begin
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begin
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if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code | after128us == 12'd1279 )
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if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code | after128us == 12'd1279 )
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begin
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begin
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next_state_fsm = error_reset;
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next_state_fsm = error_reset;
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end
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end
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else if(rx_got_null && rx_got_bit)
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else if(rx_got_null && rx_got_bit)
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begin
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begin
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next_state_fsm = connecting;
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next_state_fsm = connecting;
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end
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end
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end
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end
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connecting:
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connecting:
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begin
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begin
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if(rx_error | rx_got_nchar | rx_got_time_code | after128us == 12'd1279 )
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if(rx_error | rx_got_nchar | rx_got_time_code | after128us == 12'd1279 )
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begin
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begin
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next_state_fsm = error_reset;
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next_state_fsm = error_reset;
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end
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end
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else if(rx_got_fct)
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else if(rx_got_fct)
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begin
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begin
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next_state_fsm = run;
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next_state_fsm = run;
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end
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end
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end
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end
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run:
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run:
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begin
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begin
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if(rx_error | rx_credit_error | link_disable | after850ns == 12'd85)
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if(rx_error | rx_credit_error | link_disable | after850ns == 12'd85)
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begin
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begin
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next_state_fsm = error_reset;
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next_state_fsm = error_reset;
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end
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end
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else
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else
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begin
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begin
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next_state_fsm = run;
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next_state_fsm = run;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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always@(posedge pclk)
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always@(posedge pclk)
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begin
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begin
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if(!resetn)
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if(!resetn)
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begin
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begin
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state_fsm <= error_reset;
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state_fsm <= error_reset;
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end
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end
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else
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else
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begin
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begin
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state_fsm <= next_state_fsm;
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state_fsm <= next_state_fsm;
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case(state_fsm)
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case(state_fsm)
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error_reset:
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error_reset:
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begin
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begin
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end
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end
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error_wait:
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error_wait:
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begin
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begin
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end
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end
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ready:
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ready:
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begin
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begin
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end
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end
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started:
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started:
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begin
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begin
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end
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end
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connecting:
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connecting:
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begin
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begin
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end
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end
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run:
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run:
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begin
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begin
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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always@(posedge pclk)
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always@(posedge pclk)
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begin
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begin
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if(!resetn)
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if(!resetn)
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begin
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begin
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after128us <= 12'd0;
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after128us <= 12'd0;
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end
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end
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else
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else
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begin
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begin
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if(state_fsm == error_wait | state_fsm == started | state_fsm == connecting)
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if(state_fsm == error_wait | state_fsm == started | state_fsm == connecting)
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begin
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begin
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if(after128us < 12'd1279)
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if(after128us < 12'd1279)
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after128us <= after128us + 12'd1;
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after128us <= after128us + 12'd1;
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else
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else
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after128us <= 12'd0;
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after128us <= 12'd0;
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end
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end
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else
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else
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begin
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begin
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after128us <= 12'd0;
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after128us <= 12'd0;
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end
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end
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end
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end
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end
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end
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always@(posedge pclk)
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always@(posedge pclk)
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begin
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begin
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if(!resetn)
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if(!resetn)
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begin
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begin
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after64us <= 12'd0;
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after64us <= 12'd0;
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end
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end
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else
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else
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begin
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begin
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if(state_fsm == error_reset && (auto_start | link_start))
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if(state_fsm == error_reset && (auto_start | link_start))
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begin
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begin
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if(after64us < 12'd639)
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if(after64us < 12'd639)
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after64us <= after64us + 12'd1;
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after64us <= after64us + 12'd1;
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else
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else
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after64us <= 12'd0;
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after64us <= 12'd0;
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end
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end
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else
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else
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begin
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begin
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after64us <= 12'd0;
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after64us <= 12'd0;
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end
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end
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end
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end
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end
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end
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always@(posedge pclk)
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always@(posedge pclk)
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begin
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begin
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if(!resetn | rx_got_bit)
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if(!resetn)
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begin
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after850ns <= 12'd0;
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end
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else
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begin
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if(rx_got_bit)
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begin
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begin
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after850ns <= 12'd0;
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after850ns <= 12'd0;
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end
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end
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else
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else
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begin
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begin
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if(after850ns < 12'd85 && state_fsm == run)
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if(after850ns < 12'd85 && state_fsm == run)
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after850ns <= after850ns + 12'd1;
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after850ns <= after850ns + 12'd1;
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else
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else
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after850ns <= 12'd0;
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after850ns <= 12'd0;
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end
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end
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end
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end
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end
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endmodule
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endmodule
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