//+FHDR------------------------------------------------------------------------
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//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//FILE NAME :
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//FILE NAME :
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//DEPARTMENT : IC Design / Verification
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//DEPARTMENT : IC Design / Verification
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAMETERS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH [32,16] : width of the data : 32:
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//e.g.DATA_WIDTH [32,16] : width of the data : 32:
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//REUSE ISSUES
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//Reset Strategy :
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//Reset Strategy :
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//Clock Domains :
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//Clock Domains :
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//Critical Timing :
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//Critical Timing :
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//Test Features :
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//Test Features :
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//Asynchronous I/F :
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//Asynchronous I/F :
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//Scan Methodology :
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//Scan Methodology :
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//Instantiations :
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//Instantiations :
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//Synthesizable (y/n) :
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//Synthesizable (y/n) :
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//Other :
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//Other :
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//-FHDR------------------------------------------------------------------------
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//-FHDR------------------------------------------------------------------------
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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|
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module FSM_SPW (
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module FSM_SPW (
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input pclk,
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input pclk,
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input resetn,
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input resetn,
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|
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//fsm status control
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//fsm status control
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input auto_start,
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input auto_start,
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input link_start,
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input link_start,
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input link_disable,
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input link_disable,
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|
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//rx status input control
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//rx status input control
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input rx_error,
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input rx_error,
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input rx_credit_error,
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input rx_credit_error,
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input rx_got_bit,
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input rx_got_bit,
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input rx_got_null,
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input rx_got_null,
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input rx_got_nchar,
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input rx_got_nchar,
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input rx_got_time_code,
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input rx_got_time_code,
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input rx_got_fct,
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input rx_got_fct,
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output reg rx_resetn,
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output reg rx_resetn,
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|
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//tx status control
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//tx status control
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output reg enable_tx,
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output reg enable_tx,
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output reg send_null_tx,
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output reg send_null_tx,
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output reg send_fct_tx,
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output reg send_fct_tx,
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|
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output [5:0] fsm_state
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output [5:0] fsm_state
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);
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);
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localparam [5:0] error_reset = 6'b00_0000,
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localparam [5:0] error_reset = 6'b00_0000,
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error_wait = 6'b00_0001,
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error_wait = 6'b00_0001,
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ready = 6'b00_0010,
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ready = 6'b00_0010,
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started = 6'b00_0100,
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started = 6'b00_0100,
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connecting = 6'b00_1000,
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connecting = 6'b00_1000,
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run = 6'b01_0000;
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run = 6'b01_0000;
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|
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reg [5:0] state_fsm;
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reg [5:0] state_fsm;
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reg [5:0] next_state_fsm;
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reg [5:0] next_state_fsm;
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|
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reg [11:0] after128us;
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reg [11:0] after128us;
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reg [11:0] after64us;
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reg [11:0] after64us;
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reg [11:0] after850ns;
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reg [11:0] after850ns;
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reg got_bit_internal;
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reg got_bit_internal;
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reg get_rx_got_fct_a, get_rx_got_fct_b;
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reg get_rx_error_a, get_rx_error_b;
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reg get_rx_got_null_a, get_rx_got_null_b;
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reg get_rx_got_nchar_a, get_rx_got_nchar_b;
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reg get_rx_got_time_code_a, get_rx_got_time_code_b;
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reg get_rx_credit_error_a, get_rx_credit_error_b;
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|
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//
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//
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assign fsm_state = state_fsm;
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assign fsm_state = state_fsm;
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|
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always@(*)
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always@(*)
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begin
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begin
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next_state_fsm = state_fsm;
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next_state_fsm = state_fsm;
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|
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case(state_fsm)
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case(state_fsm)
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error_reset:
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error_reset:
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begin
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begin
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|
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if(after64us == 12'd639)
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if(after64us == 12'd639)
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begin
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begin
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next_state_fsm = error_wait;
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next_state_fsm = error_wait;
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end
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end
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else
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else
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begin
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begin
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next_state_fsm = error_reset;
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next_state_fsm = error_reset;
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end
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end
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|
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end
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end
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error_wait:
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error_wait:
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begin
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begin
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|
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if(after128us == 12'd1279)
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if(after128us == 12'd1279)
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begin
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begin
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next_state_fsm = ready;
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next_state_fsm = ready;
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end
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end
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else if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code)
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else if(get_rx_error_a | get_rx_got_fct_a | get_rx_got_nchar_a | rx_got_time_code)
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begin
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begin
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next_state_fsm = error_reset;
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next_state_fsm = error_reset;
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end
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end
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|
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end
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end
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ready:
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ready:
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begin
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begin
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|
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if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code)
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if(get_rx_error_a | get_rx_got_fct_a | get_rx_got_nchar_a | get_rx_got_time_code_a)
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begin
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begin
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next_state_fsm = error_reset;
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next_state_fsm = error_reset;
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end
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end
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else if(((!link_disable) & (link_start |(auto_start & rx_got_null)))==1'b1)
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else if(((!link_disable) & (link_start |(auto_start & get_rx_got_null_a)))==1'b1)
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begin
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begin
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next_state_fsm = started;
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next_state_fsm = started;
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end
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end
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|
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end
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end
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started:
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started:
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begin
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begin
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|
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if(rx_error | rx_got_fct | rx_got_nchar | rx_got_time_code | after128us == 12'd1279)
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if(get_rx_error_a | get_rx_got_fct_a | get_rx_got_nchar_a | get_rx_got_time_code_a | after128us == 12'd1279)
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begin
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begin
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next_state_fsm = error_reset;
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next_state_fsm = error_reset;
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end
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end
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else if((rx_got_null & rx_got_bit)== 1'b1)
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else if((get_rx_got_null_a & rx_got_bit)== 1'b1)
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begin
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begin
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next_state_fsm = connecting;
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next_state_fsm = connecting;
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end
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end
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|
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end
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end
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connecting:
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connecting:
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begin
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begin
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|
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if(rx_error | rx_got_nchar | rx_got_time_code | after128us == 12'd1279)
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if(get_rx_error_a | get_rx_got_nchar_a | get_rx_got_time_code_a | after128us == 12'd1279)
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begin
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begin
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next_state_fsm = error_reset;
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next_state_fsm = error_reset;
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end
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end
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else if(rx_got_fct)
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else if(get_rx_got_fct_a)
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begin
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begin
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next_state_fsm = run;
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next_state_fsm = run;
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end
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end
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|
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end
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end
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run:
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run:
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begin
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begin
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|
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if(rx_error | rx_credit_error | link_disable | after850ns == 12'd85)
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if(get_rx_error_a | get_rx_credit_error_a | link_disable | after850ns == 12'd85)
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begin
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begin
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next_state_fsm = error_reset;
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next_state_fsm = error_reset;
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end
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end
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else
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else
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begin
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begin
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next_state_fsm = run;
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next_state_fsm = run;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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always@(posedge pclk or negedge resetn)
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always@(posedge pclk or negedge resetn)
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begin
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begin
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if(!resetn)
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if(!resetn)
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begin
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begin
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state_fsm <= error_reset;
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state_fsm <= error_reset;
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rx_resetn <= 1'b0;
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rx_resetn <= 1'b0;
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enable_tx<= 1'b0;
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enable_tx <= 1'b0;
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send_null_tx<= 1'b0;
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send_null_tx <= 1'b0;
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send_fct_tx<= 1'b0;
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send_fct_tx<= 1'b0;
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get_rx_got_fct_a <= 1'b0;
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get_rx_got_fct_b <= 1'b0;
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get_rx_error_a <= 1'b0;
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get_rx_error_b <= 1'b0;
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get_rx_got_null_a <= 1'b0;
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get_rx_got_null_b <= 1'b0;
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get_rx_got_nchar_a <= 1'b0;
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get_rx_got_nchar_b <= 1'b0;
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get_rx_got_time_code_a <= 1'b0;
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get_rx_got_time_code_b <= 1'b0;
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get_rx_credit_error_a <= 1'b0;
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get_rx_credit_error_b <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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get_rx_got_fct_b <= rx_got_fct;
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get_rx_got_fct_a <= get_rx_got_fct_b;
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get_rx_error_b <= rx_error;
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get_rx_error_a <= get_rx_error_b;
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get_rx_got_null_b <= rx_got_null;
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get_rx_got_null_a <= get_rx_got_null_b;
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get_rx_got_nchar_b <= rx_got_nchar;
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get_rx_got_nchar_a <= get_rx_got_nchar_b;
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get_rx_got_time_code_b <= rx_got_time_code;
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get_rx_got_time_code_a <= get_rx_got_time_code_b;
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get_rx_credit_error_b <= rx_credit_error;
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get_rx_credit_error_a <= get_rx_credit_error_b;
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state_fsm <= next_state_fsm;
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state_fsm <= next_state_fsm;
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case(state_fsm)
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case(state_fsm)
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error_reset:
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error_reset:
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begin
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begin
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enable_tx<= 1'b0;
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enable_tx<= 1'b0;
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send_null_tx<= 1'b0;
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send_null_tx<= 1'b0;
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send_fct_tx<= 1'b0;
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send_fct_tx<= 1'b0;
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if(after64us == 12'd639)
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if(after64us == 12'd639)
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rx_resetn <= 1'b1;
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rx_resetn <= 1'b1;
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else
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else
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rx_resetn <= 1'b0;
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rx_resetn <= 1'b0;
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end
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end
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error_wait:
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error_wait:
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begin
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begin
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rx_resetn <= 1'b1;
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rx_resetn <= 1'b1;
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enable_tx<= 1'b0;
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enable_tx<= 1'b0;
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send_null_tx<= 1'b0;
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send_null_tx<= 1'b0;
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send_fct_tx<= 1'b0;
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send_fct_tx<= 1'b0;
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end
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end
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ready:
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ready:
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begin
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begin
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rx_resetn <= 1'b1;
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rx_resetn <= 1'b1;
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enable_tx<= 1'b1;
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enable_tx<= 1'b1;
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send_null_tx<= 1'b0;
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send_null_tx<= 1'b0;
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send_fct_tx<= 1'b0;
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send_fct_tx<= 1'b0;
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end
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end
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started:
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started:
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begin
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begin
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rx_resetn <= 1'b1;
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rx_resetn <= 1'b1;
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enable_tx<= 1'b1;
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enable_tx<= 1'b1;
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send_null_tx<= 1'b1;
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send_null_tx<= 1'b1;
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send_fct_tx<= 1'b0;
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send_fct_tx<= 1'b0;
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end
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end
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connecting:
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connecting:
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begin
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begin
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rx_resetn <= 1'b1;
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rx_resetn <= 1'b1;
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enable_tx<= 1'b1;
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enable_tx<= 1'b1;
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send_null_tx<= 1'b1;
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send_null_tx<= 1'b1;
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send_fct_tx<= 1'b1;
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send_fct_tx<= 1'b1;
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end
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end
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run:
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run:
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begin
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begin
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rx_resetn <= 1'b1;
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rx_resetn <= 1'b1;
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enable_tx<= 1'b1;
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enable_tx<= 1'b1;
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send_null_tx<= 1'b1;
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send_null_tx<= 1'b1;
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send_fct_tx<= 1'b1;
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send_fct_tx<= 1'b1;
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end
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end
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endcase
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endcase
|
|
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end
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end
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end
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end
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|
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always@(posedge pclk)
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always@(posedge pclk)
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begin
|
begin
|
|
|
if(!resetn || state_fsm == error_reset)
|
if(!resetn || state_fsm == error_reset)
|
begin
|
begin
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after128us <= 12'd0;
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after128us <= 12'd0;
|
end
|
end
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else
|
else
|
begin
|
begin
|
|
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if(next_state_fsm == connecting && state_fsm == started)
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if(next_state_fsm == connecting && state_fsm == started)
|
begin
|
begin
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after128us <= 12'd0;
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after128us <= 12'd0;
|
end
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end
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else if(state_fsm == error_wait || state_fsm == started || state_fsm == connecting)
|
else if(state_fsm == error_wait || state_fsm == started || state_fsm == connecting)
|
begin
|
begin
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if(after128us < 12'd1279)
|
if(after128us < 12'd1279)
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after128us <= after128us + 12'd1;
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after128us <= after128us + 12'd1;
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else
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else
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after128us <= 12'd0;
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after128us <= 12'd0;
|
end
|
end
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else
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else
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begin
|
begin
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after128us <= 12'd0;
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after128us <= 12'd0;
|
end
|
end
|
end
|
end
|
|
|
end
|
end
|
|
|
always@(posedge pclk)
|
always@(posedge pclk)
|
begin
|
begin
|
|
|
if(!resetn)
|
if(!resetn)
|
begin
|
begin
|
after64us <= 12'd0;
|
after64us <= 12'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(state_fsm == error_reset && (auto_start | link_start))
|
if(state_fsm == error_reset && (auto_start | link_start))
|
begin
|
begin
|
if(after64us < 12'd639)
|
if(after64us < 12'd639)
|
after64us <= after64us + 12'd1;
|
after64us <= after64us + 12'd1;
|
else
|
else
|
after64us <= 12'd0;
|
after64us <= 12'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
after64us <= 12'd0;
|
after64us <= 12'd0;
|
end
|
end
|
end
|
end
|
|
|
end
|
end
|
|
|
always@(posedge pclk)
|
always@(posedge pclk)
|
begin
|
begin
|
if(!resetn)
|
if(!resetn)
|
begin
|
begin
|
got_bit_internal <= 1'b0;
|
got_bit_internal <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(rx_got_bit)
|
if(rx_got_bit)
|
got_bit_internal <= 1'b1;
|
got_bit_internal <= 1'b1;
|
else
|
else
|
got_bit_internal <= 1'b0;
|
got_bit_internal <= 1'b0;
|
end
|
end
|
end
|
end
|
|
|
always@(posedge pclk)
|
always@(posedge pclk)
|
begin
|
begin
|
|
|
if(!resetn | got_bit_internal)
|
if(!resetn | got_bit_internal)
|
begin
|
begin
|
after850ns <= 12'd0;
|
after850ns <= 12'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(state_fsm != run)
|
if(state_fsm != run)
|
begin
|
begin
|
after850ns <= 12'd0;
|
after850ns <= 12'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(after850ns < 12'd85 && state_fsm == run)
|
if(after850ns < 12'd85 && state_fsm == run)
|
after850ns <= after850ns + 12'd1;
|
after850ns <= after850ns + 12'd1;
|
else
|
else
|
after850ns <= after850ns;
|
after850ns <= after850ns;
|
|
|
end
|
end
|
end
|
end
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
