//+FHDR------------------------------------------------------------------------
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//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//FILE NAME :
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//FILE NAME :
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//DEPARTMENT : IC Design / Verification
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//DEPARTMENT : IC Design / Verification
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAMETERS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH [32,16] : width of the data : 32:
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//e.g.DATA_WIDTH [32,16] : width of the data : 32:
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//REUSE ISSUES
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//Reset Strategy :
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//Reset Strategy :
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//Clock Domains :
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//Clock Domains :
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//Critical Timing :
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//Critical Timing :
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//Test Features :
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//Test Features :
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//Asynchronous I/F :
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//Asynchronous I/F :
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//Scan Methodology :
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//Scan Methodology :
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//Instantiations :
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//Instantiations :
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//Synthesizable (y/n) :
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//Synthesizable (y/n) :
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//Other :
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//Other :
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//-FHDR------------------------------------------------------------------------
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//-FHDR------------------------------------------------------------------------
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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|
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module RX_SPW (
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module RX_SPW (
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input rx_din,
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input rx_din,
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input rx_sin,
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input rx_sin,
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|
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input rx_resetn,
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input rx_resetn,
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|
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output rx_error,
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output rx_error,
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|
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output rx_got_bit,
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output rx_got_bit,
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output rx_got_null,
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output rx_got_null,
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output rx_got_nchar,
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output rx_got_nchar,
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output rx_got_time_code,
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output rx_got_time_code,
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output rx_got_fct,
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output rx_got_fct,
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|
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output [8:0] rx_data_flag,
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output reg [8:0] rx_data_flag,
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output rx_buffer_write,
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output reg rx_buffer_write,
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|
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output [7:0] rx_time_out,
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output reg [7:0] rx_time_out,
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output rx_tick_out
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output reg rx_tick_out
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);
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);
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reg [4:0] counter_neg;
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reg [4:0] counter_neg;
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|
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wire posedge_clk;
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wire posedge_clk;
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wire negedge_clk;
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wire negedge_clk;
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|
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reg bit_c_0;//N
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reg bit_c_0;//N
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reg bit_c_1;//P
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reg bit_c_1;//P
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reg bit_c_2;//N
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reg bit_c_2;//N
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reg bit_c_3;//P
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reg bit_c_3;//P
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|
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reg bit_d_0;//N
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reg bit_d_0;//N
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reg bit_d_1;//P
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reg bit_d_1;//P
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reg bit_d_2;//N
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reg bit_d_2;//N
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reg bit_d_3;//P
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reg bit_d_3;//P
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reg bit_d_4;//N
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reg bit_d_4;//N
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reg bit_d_5;//P
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reg bit_d_5;//P
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reg bit_d_6;//N
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reg bit_d_6;//N
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reg bit_d_7;//P
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reg bit_d_7;//P
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reg bit_d_8;//N
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reg bit_d_8;//N
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reg bit_d_9;//P
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reg bit_d_9;//P
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|
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reg is_control;
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reg is_control;
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reg is_data;
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reg is_data;
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|
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reg last_is_control;
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reg last_is_control;
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reg last_is_data;
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reg last_is_data;
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reg last_is_timec;
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reg last_is_timec;
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|
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reg last_was_control;
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reg last_was_control;
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reg last_was_data;
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reg last_was_data;
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reg last_was_timec;
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reg last_was_timec;
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|
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reg [3:0] control;
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reg [3:0] control;
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reg [9:0] data;
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reg [9:0] data;
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reg [9:0] timecode;
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reg [9:0] timecode;
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|
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reg [3:0] control_l_r;
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reg [3:0] control_l_r;
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reg [9:0] data_l_r;
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reg [9:0] data_l_r;
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|
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reg parity_error;
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reg parity_error;
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wire check_c_d;
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wire check_c_d;
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|
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reg rx_data_take;
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//CLOCK RECOVERY
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//CLOCK RECOVERY
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assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
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assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
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assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0;
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assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0;
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|
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assign check_c_d = ((is_control & counter_neg == 5'd2) == 1'b1 | (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 | (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;
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assign check_c_d = ((is_control & counter_neg == 5'd2) == 1'b1 | (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 | (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;
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|
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assign rx_got_null = (control_l_r[2:0] == 3'd7 & control[2:0] == 3'd4)?1'b1:1'b0;
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assign rx_got_null = (control_l_r[2:0] == 3'd7 & control[2:0] == 3'd4)?1'b1:1'b0;
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assign rx_got_fct = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0;
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assign rx_got_fct = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0;
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|
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assign rx_got_bit = (posedge_clk)?1'b1:1'b0;
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assign rx_got_bit = (posedge_clk)?1'b1:1'b0;
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|
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assign rx_error = parity_error;
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assign rx_error = parity_error;
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assign rx_got_nchar = (control[2:0] != 3'd7 & is_data)?1'b1:1'b0;
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assign rx_got_nchar = (control[2:0] != 3'd7 & is_data)?1'b1:1'b0;
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assign rx_got_time_code = (control[2:0] == 3'd7 & is_data)?1'b1:1'b0;
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assign rx_got_time_code = (control[2:0] == 3'd7 & is_data)?1'b1:1'b0;
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|
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assign rx_buffer_write = ( (control[2:0] == 3'd5 & is_control) == 1'b1 | (control[2:0] != 3'd7 & is_data) == 1'b1)?1'b1:1'b0;
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assign rx_data_flag = ( (control[2:0] == 3'd6 & is_control) == 1'b1 )?9'b100000001:
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( (control[2:0] == 3'd5 & is_control) == 1'b1 )?9'b100000000:
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( (control[2:0] != 3'd7 & is_data) == 1'b1)?data[8:0]:9'd0;
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assign rx_time_out = ((control[2:0] == 3'd7 & is_data) == 1'b1)?timecode[7:0]:8'd0;
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assign rx_tick_out = ((control[2:0] == 3'd7 & is_data) == 1'b1)?1'b1:1'b0;
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always@(posedge posedge_clk or negedge rx_resetn)
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always@(posedge posedge_clk or negedge rx_resetn)
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begin
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begin
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|
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if(!rx_resetn)
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if(!rx_resetn)
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begin
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begin
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bit_c_1 <= 1'b0;
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bit_c_1 <= 1'b0;
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bit_c_3 <= 1'b0;
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bit_c_3 <= 1'b0;
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bit_d_1 <= 1'b0;
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bit_d_1 <= 1'b0;
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bit_d_3 <= 1'b0;
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bit_d_3 <= 1'b0;
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bit_d_5 <= 1'b0;
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bit_d_5 <= 1'b0;
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bit_d_7 <= 1'b0;
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bit_d_7 <= 1'b0;
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bit_d_9 <= 1'b0;
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bit_d_9 <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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bit_c_1 <= rx_din;
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bit_c_1 <= rx_din;
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bit_c_3 <= bit_c_1;
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bit_c_3 <= bit_c_1;
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bit_d_1 <= rx_din;
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bit_d_1 <= rx_din;
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bit_d_3 <= bit_d_1;
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bit_d_3 <= bit_d_1;
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bit_d_5 <= bit_d_3;
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bit_d_5 <= bit_d_3;
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bit_d_7 <= bit_d_5;
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bit_d_7 <= bit_d_5;
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bit_d_9 <= bit_d_7;
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bit_d_9 <= bit_d_7;
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|
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end
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end
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end
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end
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always@(posedge negedge_clk or negedge rx_resetn)
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always@(posedge negedge_clk or negedge rx_resetn)
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begin
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begin
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|
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if(!rx_resetn)
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if(!rx_resetn)
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begin
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begin
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bit_c_0 <= 1'b0;
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bit_c_0 <= 1'b0;
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bit_c_2 <= 1'b0;
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bit_c_2 <= 1'b0;
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bit_d_0 <= 1'b0;
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bit_d_0 <= 1'b0;
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bit_d_2 <= 1'b0;
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bit_d_2 <= 1'b0;
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bit_d_4 <= 1'b0;
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bit_d_4 <= 1'b0;
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bit_d_6 <= 1'b0;
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bit_d_6 <= 1'b0;
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bit_d_8 <= 1'b0;
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bit_d_8 <= 1'b0;
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is_control <= 1'b0;
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is_control <= 1'b0;
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is_data <= 1'b0;
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is_data <= 1'b0;
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counter_neg <= 5'd0;
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counter_neg <= 5'd0;
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end
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end
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else
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else
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begin
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begin
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|
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bit_c_0 <= rx_din;
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bit_c_0 <= rx_din;
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bit_c_2 <= bit_c_0;
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bit_c_2 <= bit_c_0;
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bit_d_0 <= rx_din;
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bit_d_0 <= rx_din;
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bit_d_2 <= bit_d_0;
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bit_d_2 <= bit_d_0;
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bit_d_4 <= bit_d_2;
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bit_d_4 <= bit_d_2;
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bit_d_6 <= bit_d_4;
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bit_d_6 <= bit_d_4;
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bit_d_8 <= bit_d_6;
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bit_d_8 <= bit_d_6;
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if(counter_neg == 5'd1)
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if(counter_neg == 5'd1)
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begin
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begin
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if(bit_c_0)
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if(bit_c_0)
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begin
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begin
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is_control <= 1'b1;
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is_control <= 1'b1;
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is_data <= 1'b0;
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is_data <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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is_control <= 1'b0;
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is_control <= 1'b0;
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is_data <= 1'b1;
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is_data <= 1'b1;
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end
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end
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counter_neg <= counter_neg + 5'd1;
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counter_neg <= counter_neg + 5'd1;
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end
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end
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else
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else
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begin
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begin
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if(is_control)
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if(is_control)
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begin
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begin
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if(counter_neg == 5'd2)
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if(counter_neg == 5'd2)
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begin
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begin
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counter_neg <= 5'd1;
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counter_neg <= 5'd1;
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is_control <= 1'b0;
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is_control <= 1'b0;
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end
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end
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else
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else
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counter_neg <= counter_neg + 5'd1;
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counter_neg <= counter_neg + 5'd1;
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end
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end
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else if(is_data)
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else if(is_data)
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begin
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begin
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if(counter_neg == 5'd5)
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if(counter_neg == 5'd5)
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begin
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begin
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counter_neg <= 5'd1;
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counter_neg <= 5'd1;
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is_data <= 1'b0;
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is_data <= 1'b0;
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end
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end
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else
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else
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counter_neg <= counter_neg + 5'd1;
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counter_neg <= counter_neg + 5'd1;
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end
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end
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else
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else
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begin
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begin
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counter_neg <= counter_neg + 5'd1;
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counter_neg <= counter_neg + 5'd1;
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end
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end
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end
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end
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end
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end
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end
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end
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always@(*)
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always@(*)
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begin
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begin
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|
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parity_error = 1'b0;
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parity_error = 1'b0;
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if(last_is_control)
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if(last_is_control)
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begin
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begin
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if(last_was_control)
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if(last_was_control)
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begin
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begin
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if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
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if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
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begin
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begin
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parity_error = 1'b1;
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parity_error = 1'b1;
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end
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end
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end
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end
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else if(last_was_timec)
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else if(last_was_timec)
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begin
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begin
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if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])
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if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])
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begin
|
begin
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parity_error = 1'b1;
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parity_error = 1'b1;
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end
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end
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end
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end
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else if(last_was_data)
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else if(last_was_data)
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begin
|
begin
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if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
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if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
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begin
|
begin
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parity_error = 1'b1;
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parity_error = 1'b1;
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end
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end
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end
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end
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end
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end
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else if(last_is_data)
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else if(last_is_data)
|
begin
|
begin
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if(last_was_control)
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if(last_was_control)
|
begin
|
begin
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if(!(data[8]^control[1]^control[0]) != data[9])
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if(!(data[8]^control[1]^control[0]) != data[9])
|
begin
|
begin
|
parity_error = 1'b1;
|
parity_error = 1'b1;
|
end
|
end
|
end
|
end
|
else if(last_was_timec)
|
else if(last_was_timec)
|
begin
|
begin
|
if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])
|
if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])
|
begin
|
begin
|
parity_error = 1'b1;
|
parity_error = 1'b1;
|
end
|
end
|
end
|
end
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else if(last_was_data)
|
else if(last_was_data)
|
begin
|
begin
|
if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
|
if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
|
begin
|
begin
|
parity_error = 1'b1;
|
parity_error = 1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
end
|
end
|
|
|
always@(posedge check_c_d or negedge rx_resetn )
|
always@(posedge check_c_d or negedge rx_resetn )
|
begin
|
begin
|
|
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
control <= 4'd0;
|
control <= 4'd0;
|
control_l_r <= 4'd0;
|
control_l_r <= 4'd0;
|
|
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data <= 10'd0;
|
data <= 10'd0;
|
data_l_r <= 10'd0;
|
data_l_r <= 10'd0;
|
|
rx_data_flag <= 9'd0;
|
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rx_buffer_write <= 1'b0;
|
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rx_data_take <= 1'b0;
|
|
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timecode <= 10'd0;
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timecode <= 10'd0;
|
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rx_time_out <= 8'd0;
|
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rx_tick_out <= 1'b0;
|
|
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last_is_control <=1'b0;
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last_is_control <=1'b0;
|
last_is_data <=1'b0;
|
last_is_data <=1'b0;
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last_is_timec <=1'b0;
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last_is_timec <=1'b0;
|
|
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last_was_control <=1'b0;
|
last_was_control <=1'b0;
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last_was_data <=1'b0;
|
last_was_data <=1'b0;
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last_was_timec <=1'b0;
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last_was_timec <=1'b0;
|
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
|
rx_buffer_write <= rx_data_take;
|
|
rx_data_flag <= data[8:0];
|
|
|
|
rx_time_out <= timecode;
|
|
|
if((control[2:0] != 3'd7 & is_data) == 1'b1)
|
if((control[2:0] != 3'd7 & is_data) == 1'b1)
|
begin
|
begin
|
|
|
data <= {bit_d_9,bit_d_8,bit_d_7,bit_d_6,bit_d_5,bit_d_4,bit_d_3,bit_d_2,bit_d_1,bit_d_0};
|
data <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
|
data_l_r <= data;
|
data_l_r <= data;
|
|
|
|
rx_data_take <= 1'b1;
|
|
rx_tick_out <= 1'b0;
|
|
|
last_is_control <=1'b0;
|
last_is_control <=1'b0;
|
last_is_data <=1'b1;
|
last_is_data <=1'b1;
|
last_is_timec <=1'b0;
|
last_is_timec <=1'b0;
|
last_was_control <= last_is_control;
|
last_was_control <= last_is_control;
|
last_was_data <= last_is_data ;
|
last_was_data <= last_is_data ;
|
last_was_timec <= last_is_timec;
|
last_was_timec <= last_is_timec;
|
end
|
end
|
else if((control[2:0] == 3'd7 & is_data) == 1'b1)
|
else if((control[2:0] == 3'd7 & is_data) == 1'b1)
|
begin
|
begin
|
|
|
timecode <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
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timecode <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
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rx_tick_out <= 1'b1;
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rx_data_take <= 1'b0;
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|
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last_is_control <= 1'b0;
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last_is_control <= 1'b0;
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last_is_data <= 1'b0;
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last_is_data <= 1'b0;
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last_is_timec <= 1'b1;
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last_is_timec <= 1'b1;
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last_was_control <= last_is_control;
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last_was_control <= last_is_control;
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last_was_data <= last_is_data ;
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last_was_data <= last_is_data ;
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last_was_timec <= last_is_timec;
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last_was_timec <= last_is_timec;
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end
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end
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else if({bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd6 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd13 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd5 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd15 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd7 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd4 | | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd12)
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else if({bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd6 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd13 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd5 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd15 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd7 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd4 | | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd12)
|
begin
|
begin
|
|
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control <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
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control <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
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control_l_r <= control[3:0];
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control_l_r <= control[3:0];
|
|
|
/*
|
if((control[2:0] == 3'd6 & is_control) == 1'b1 )
|
if(last_is_data & last_was_data)
|
begin
|
begin
|
data <= 10'b0100000001;
|
data <= 10'd0;
|
rx_data_take <= 1'b1;
|
data_l_r <= 10'd0;
|
end
|
timecode <= 10'd0;
|
else if( (control[2:0] == 3'd5 & is_control) == 1'b1 )
|
end
|
begin
|
*/
|
data <= 10'b0100000000;
|
|
rx_data_take <= 1'b1;
|
|
end
|
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else
|
|
begin
|
|
rx_data_take <= 1'b0;
|
|
end
|
|
|
|
rx_tick_out <= 1'b0;
|
|
|
last_is_control <= 1'b1;
|
last_is_control <= 1'b1;
|
last_is_data <= 1'b0;
|
last_is_data <= 1'b0;
|
last_is_timec <= 1'b0;
|
last_is_timec <= 1'b0;
|
last_was_control <= last_is_control;
|
last_was_control <= last_is_control;
|
last_was_data <= last_is_data ;
|
last_was_data <= last_is_data ;
|
last_was_timec <= last_is_timec;
|
last_was_timec <= last_is_timec;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
endmodule
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endmodule
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|
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