//+FHDR------------------------------------------------------------------------
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//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//FILE NAME :
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//FILE NAME :
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//DEPARTMENT : IC Design / Verification
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//DEPARTMENT : IC Design / Verification
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAMETERS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH [32,16] : width of the data : 32:
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//e.g.DATA_WIDTH [32,16] : width of the data : 32:
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//REUSE ISSUES
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//Reset Strategy :
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//Reset Strategy :
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//Clock Domains :
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//Clock Domains :
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//Critical Timing :
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//Critical Timing :
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//Test Features :
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//Test Features :
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//Asynchronous I/F :
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//Asynchronous I/F :
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//Scan Methodology :
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//Scan Methodology :
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//Instantiations :
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//Instantiations :
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//Synthesizable (y/n) :
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//Synthesizable (y/n) :
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//Other :
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//Other :
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//-FHDR------------------------------------------------------------------------
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//-FHDR------------------------------------------------------------------------
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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module top_spw_ultra_light(
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module top_spw_ultra_light(
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input pclk,
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input pclk,
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input ppllclk,
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input ppllclk,
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input resetn,
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input resetn,
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input top_sin,
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input top_sin,
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input top_din,
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input top_din,
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input top_auto_start,
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input top_auto_start,
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input top_link_start,
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input top_link_start,
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input top_link_disable,
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input top_link_disable,
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input top_tx_write,
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input top_tx_write,
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input [8:0] top_tx_data,
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input [8:0] top_tx_data,
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input top_tx_tick,
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input top_tx_tick,
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input [7:0] top_tx_time,
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input [7:0] top_tx_time,
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input credit_error_rx,
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input credit_error_rx,
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input top_send_fct_now,
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input top_send_fct_now,
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output [8:0] datarx_flag,
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output [8:0] datarx_flag,
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output buffer_write,
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output buffer_write,
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output [7:0] time_out,
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output [7:0] time_out,
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output tick_out,
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output tick_out,
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output top_dout,
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output top_dout,
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output top_sout,
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output top_sout,
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output top_tx_ready,
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output top_tx_ready,
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output top_tx_ready_tick,
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output top_tx_ready_tick,
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output [5:0] top_fsm
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output [5:0] top_fsm
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);
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);
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wire resetn_rx;
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wire resetn_rx;
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wire error_rx;
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wire error_rx;
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wire got_bit_rx;
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wire got_bit_rx;
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wire got_null_rx;
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wire got_null_rx;
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wire got_nchar_rx;
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wire got_nchar_rx;
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wire got_time_code_rx;
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wire got_time_code_rx;
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wire got_fct_rx;
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wire got_fct_rx;
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wire enable_tx;
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wire enable_tx;
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wire send_null_tx;
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wire send_null_tx;
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wire send_fct_tx;
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wire send_fct_tx;
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wire got_fct_flag_fsm;
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wire got_fct_flag_fsm;
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FSM_SPW FSM(
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FSM_SPW FSM(
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.pclk(pclk),
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.pclk(pclk),
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.resetn(resetn),
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.resetn(resetn),
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.auto_start(top_auto_start),
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.auto_start(top_auto_start),
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.link_start(top_link_start),
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.link_start(top_link_start),
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.link_disable(top_link_disable),
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.link_disable(top_link_disable),
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.rx_error(error_rx),
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.rx_error(error_rx),
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.rx_credit_error(credit_error_rx),
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.rx_credit_error(credit_error_rx),
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.rx_got_bit(got_bit_rx),
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.rx_got_bit(got_bit_rx),
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.rx_got_null(got_null_rx),
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.rx_got_null(got_null_rx),
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.rx_got_nchar(got_nchar_rx),
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.rx_got_nchar(got_nchar_rx),
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.rx_got_time_code(got_time_code_rx),
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.rx_got_time_code(got_time_code_rx),
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.rx_got_fct(got_fct_flag_fsm),
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.rx_got_fct(got_fct_flag_fsm),
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.rx_resetn(resetn_rx),
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.rx_resetn(resetn_rx),
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.enable_tx(enable_tx),
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.enable_tx(enable_tx),
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.send_null_tx(send_null_tx),
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.send_null_tx(send_null_tx),
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.send_fct_tx(send_fct_tx),
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.send_fct_tx(send_fct_tx),
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.fsm_state(top_fsm)
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.fsm_state(top_fsm)
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);
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);
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RX_SPW RX(
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RX_SPW RX(
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.rx_din(top_din),
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.rx_din(top_din),
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.rx_sin(top_sin),
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.rx_sin(top_sin),
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.rx_resetn(resetn_rx),
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.rx_resetn(resetn_rx),
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.rx_error(error_rx),
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.rx_error(error_rx),
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.rx_got_bit(got_bit_rx),
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.rx_got_bit(got_bit_rx),
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.rx_got_null(got_null_rx),
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.rx_got_null(got_null_rx),
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.rx_got_nchar(got_nchar_rx),
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.rx_got_nchar(got_nchar_rx),
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.rx_got_time_code(got_time_code_rx),
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.rx_got_time_code(got_time_code_rx),
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.rx_got_fct(got_fct_rx),
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.rx_got_fct(got_fct_rx),
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.rx_got_fct_fsm(got_fct_flag_fsm),
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.rx_got_fct_fsm(got_fct_flag_fsm),
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.rx_data_flag(datarx_flag),
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.rx_data_flag(datarx_flag),
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.rx_buffer_write(buffer_write),
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.rx_buffer_write(buffer_write),
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.rx_time_out(time_out),
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.rx_time_out(time_out),
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.rx_tick_out(tick_out)
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.rx_tick_out(tick_out)
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);
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);
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TX_SPW TX(
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TX_SPW TX(
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.pclk_tx(ppllclk),
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.pclk_tx(ppllclk),
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.data_tx_i(top_tx_data),
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.data_tx_i(top_tx_data),
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.txwrite_tx(top_tx_write),
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.txwrite_tx(top_tx_write),
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.timecode_tx_i(top_tx_time),
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.timecode_tx_i(top_tx_time),
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.tickin_tx(top_tx_tick),
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.tickin_tx(top_tx_tick),
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.enable_tx(enable_tx),
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.enable_tx(enable_tx),
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.send_null_tx(send_null_tx),
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.send_null_tx(send_null_tx),
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.send_fct_tx(send_fct_tx),
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.send_fct_tx(send_fct_tx),
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.gotfct_tx(got_fct_rx),
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.gotfct_tx(got_fct_rx),
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.send_fct_now(top_send_fct_now),
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.send_fct_now(top_send_fct_now),
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.tx_dout_e(top_dout),
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.tx_dout_e(top_dout),
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.tx_sout_e(top_sout),
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.tx_sout_e(top_sout),
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.ready_tx_data(top_tx_ready),
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.ready_tx_data(top_tx_ready),
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.ready_tx_timecode(top_tx_ready_tick)
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.ready_tx_timecode(top_tx_ready_tick)
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);
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);
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endmodule
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endmodule
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