OpenCores
URL https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk

Subversion Repositories spacewiresystemc

[/] [spacewiresystemc/] [trunk/] [systemC/] [link_sc.h] - Diff between revs 5 and 12

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 5 Rev 12
#ifndef CONTROL_SC_H
#ifndef CONTROL_SC_H
#define CONTROL_SC_H
#define CONTROL_SC_H
 
 
class Control_SC
class Control_SC
{
{
        public:
        public:
        /*Constructor*/
        /*Constructor*/
        Control_SC();
        Control_SC();
 
 
        /*initialize systemC model*/
        /*initialize systemC model*/
        virtual void init();
        virtual void init();
 
 
        /*Reset the model*/
        /*Reset the model*/
        virtual bool reset_set();
        virtual bool reset_set();
 
 
        /*Run the Env for ammount off time*/
        /*Run the Env for ammount off time*/
        virtual void run_sim();
        virtual void run_sim();
 
 
        /*Tell to SystemC to finish*/
        /*Tell to SystemC to finish*/
        virtual void stop_sim();
        virtual void stop_sim();
 
 
        /*get dout */
        /*get dout */
        virtual unsigned int get_value_dout();
        virtual unsigned int get_value_dout();
        /*get sout*/
        /*get sout*/
        virtual unsigned int get_value_sout();
        virtual unsigned int get_value_sout();
 
 
        /*set sin*/
        /*set sin*/
        virtual void set_rx_sin(unsigned int strobe);
        virtual void set_rx_sin(unsigned int strobe);
        /*set din*/
        /*set din*/
        virtual void set_rx_din(unsigned int data);
        virtual void set_rx_din(unsigned int data);
 
 
        virtual unsigned int get_spw_fsm();
        virtual unsigned int get_spw_fsm();
 
 
        virtual unsigned int finish_simulation();
        virtual unsigned int finish_simulation();
 
 
        //verilog variables 
        //verilog variables 
        virtual bool verilog_linkenable();
        virtual bool verilog_linkenable();
        virtual bool verilog_autostart();
        virtual bool verilog_autostart();
        virtual bool verilog_linkdisable();
        virtual bool verilog_linkdisable();
 
        virtual float verilog_frequency();
 
 
        //tests 
        //tests 
        virtual bool start_tx_test();
        virtual bool start_tx_test();
        virtual bool enable_time_code_tx_test();
        virtual bool enable_time_code_tx_test();
        virtual void end_tx_test();
        virtual void end_tx_test();
        virtual unsigned int take_data(unsigned int a);
        virtual unsigned int take_data(unsigned int a);
        virtual int size_data_test();
        virtual int size_data_test();
 
 
        virtual void data_o(unsigned int data, unsigned int pos);
        virtual void data_o(unsigned int data, unsigned int pos);
 
 
        virtual unsigned int clock_tx();
        virtual unsigned int clock_tx();
 
 
 
 
};
};
#endif
#endif
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.