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[/] [spacewiresystemc/] [trunk/] [testbench/] [module_tb.v] - Diff between revs 7 and 12

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Rev 7 Rev 12
`timescale 1ns/1ns
`timescale 1ns/1ns
`default_nettype none
`default_nettype none
 
 
module module_tb;
module module_tb;
 
 
        reg CLK_SIM;
        reg CLK_SIM;
 
 
        `ifdef VERILOG_A
        `ifdef VERILOG_A
 
 
                /*SPWTCR*/
                /*SPWTCR*/
                wire CLOCK;
                wire CLOCK;
                reg CLK;
                reg CLK;
                wire RESETn;
                wire RESETn;
                wire LINK_START;
                wire LINK_START;
                wire LINK_DISABLE;
                wire LINK_DISABLE;
                wire AUTOSTART;
                wire AUTOSTART;
                wire [2:0] CURRENTSTATE;
                wire [2:0] CURRENTSTATE;
                wire [10:0] FLAGS;
                wire [10:0] FLAGS;
                wire [8:0] DATA_I;
                wire [8:0] DATA_I;
                wire WR_DATA;
                wire WR_DATA;
                wire TX_FULL;
                wire TX_FULL;
                wire [8:0] DATA_O;
                wire [8:0] DATA_O;
                wire RD_DATA;
                wire RD_DATA;
                wire RX_EMPTY;
                wire RX_EMPTY;
                wire TICK_OUT;
                wire TICK_OUT;
                wire [7:0] TIME_OUT;
                wire [7:0] TIME_OUT;
                wire TICK_IN;
                wire TICK_IN;
                wire [7:0] TIME_IN;
                wire [7:0] TIME_IN;
                wire [6:0] TX_CLK_DIV;
                wire [6:0] TX_CLK_DIV;
                wire SPILL_ENABLE;
                wire SPILL_ENABLE;
                wire Din;
                wire Din;
                wire Sin;
                wire Sin;
                wire Dout;
                wire Dout;
                wire Sout;
                wire Sout;
 
 
                wire [3:0] SPW_SC_FSM;
                wire [3:0] SPW_SC_FSM;
                wire [3:0] SPW_SC_FSM_OUT;
                wire [3:0] SPW_SC_FSM_OUT;
                wire RX_CLOCK_RECOVERY_SC;
                wire RX_CLOCK_RECOVERY_SC;
                wire TX_CLOCK_RECOVERY_VLOG;
                wire TX_CLOCK_RECOVERY_VLOG;
                wire TX_CLOCK_OUT;
                wire TX_CLOCK_OUT;
                wire TX_CLOCK_OUT_SC;
                wire TX_CLOCK_OUT_SC;
 
 
                assign RX_CLOCK_RECOVERY_SC = Din ^ Sin;
                assign RX_CLOCK_RECOVERY_SC = Din ^ Sin;
                assign TX_CLOCK_OUT_SC = TX_CLOCK_OUT;
                assign TX_CLOCK_OUT_SC = TX_CLOCK_OUT;
                assign SPW_SC_FSM_OUT = SPW_SC_FSM;
                assign SPW_SC_FSM_OUT = SPW_SC_FSM;
 
 
                assign TX_CLOCK_RECOVERY_VLOG = Dout ^ Sout;
                assign TX_CLOCK_RECOVERY_VLOG = Dout ^ Sout;
 
 
                assign CLOCK = CLK;
                assign CLOCK = CLK;
 
 
                initial CLK = 1'b0;
                initial CLK = 1'b0;
                always #(10) CLK = ~CLK;
                always #(10) CLK = ~CLK;
 
 
                SpwTCR DUT_TCR (
                SpwTCR DUT_TCR (
                                .CLOCK(CLOCK),
                                .CLOCK(CLOCK),
                                .RESETn(RESETn),
                                .RESETn(RESETn),
                                .LINK_START(LINK_START),
                                .LINK_START(LINK_START),
                                .LINK_DISABLE(LINK_DISABLE),
                                .LINK_DISABLE(LINK_DISABLE),
                                .AUTOSTART(AUTOSTART),
                                .AUTOSTART(AUTOSTART),
                                .CURRENTSTATE(CURRENTSTATE),
                                .CURRENTSTATE(CURRENTSTATE),
                                .FLAGS(FLAGS),
                                .FLAGS(FLAGS),
                                .DATA_I(DATA_I),
                                .DATA_I(DATA_I),
                                .WR_DATA(WR_DATA),
                                .WR_DATA(WR_DATA),
                                .TX_FULL(TX_FULL),
                                .TX_FULL(TX_FULL),
                                .DATA_O(DATA_O),
                                .DATA_O(DATA_O),
                                .RD_DATA(RD_DATA),
                                .RD_DATA(RD_DATA),
                                .RX_EMPTY(RX_EMPTY),
                                .RX_EMPTY(RX_EMPTY),
                                .TICK_OUT(TICK_OUT),
                                .TICK_OUT(TICK_OUT),
                                .TIME_OUT(TIME_OUT),
                                .TIME_OUT(TIME_OUT),
                                .TICK_IN(TICK_IN),
                                .TICK_IN(TICK_IN),
                                .TIME_IN(TIME_IN),
                                .TIME_IN(TIME_IN),
                                .TX_CLK_DIV(TX_CLK_DIV),
                                .TX_CLK_DIV(TX_CLK_DIV),
                                .SPILL_ENABLE(SPILL_ENABLE),
                                .SPILL_ENABLE(SPILL_ENABLE),
                                .Din(Din),
                                .Din(Din),
                                .Sin(Sin),
                                .Sin(Sin),
                                .Dout(Dout),
                                .Dout(Dout),
                                .Sout(Sout)
                                .Sout(Sout)
                        );
                        );
 
 
 
 
                        always@(posedge CLK , negedge CLK)
                        always@(posedge CLK , negedge CLK)
                                $global_reset;
                                $global_reset;
 
 
                        always@(posedge CLK)
                        always@(posedge CLK)
                                $write_tx_spw;
                                $write_tx_spw;
 
 
                        always@(posedge CLK)
                        always@(posedge CLK)
                                $receive_rx_spw;
                                $receive_rx_spw;
 
 
                        //FLAG USED TO FINISH SIMULATION PROGRAM 
                        //FLAG USED TO FINISH SIMULATION PROGRAM 
                        always@(posedge CLK)
                        always@(posedge CLK)
                        begin
                        begin
                                wait(i == 1);
                                wait(i == 1);
                                $finish();
                                $finish();
                        end
                        end
        `endif
        `endif
 
 
        `ifdef VERILOG_B
        `ifdef VERILOG_B
         `endif
         `endif
 
 
                integer time_clk_ns;
                integer time_clk_ns;
 
 
                reg PCLK;
                reg PCLK;
                reg PPLLCLK;
                reg PPLLCLK;
 
 
                wire RESETN;
                wire RESETN;
 
 
                wire TOP_SIN;
                wire TOP_SIN;
                wire TOP_DIN;
                wire TOP_DIN;
 
 
                wire AUTO_START;
                wire AUTO_START;
                wire LINK_START;
                wire LINK_START;
                wire LINK_DISABLE;
                wire LINK_DISABLE;
 
 
                wire TOP_TX_WRITE;
                wire TOP_TX_WRITE;
                wire [8:0] TOP_TX_DATA;
                wire [8:0] TOP_TX_DATA;
 
 
                wire TOP_TX_TICK;
                wire TOP_TX_TICK;
                wire [7:0] TOP_TX_TIME;
                wire [7:0] TOP_TX_TIME;
 
 
                wire CREDIT_ERROR_RX;
                wire CREDIT_ERROR_RX;
                wire TOP_SEND_FCT_NOW;
                wire TOP_SEND_FCT_NOW;
 
 
                wire [8:0] DATARX_FLAG;
                wire [8:0] DATARX_FLAG;
                wire BUFFER_WRITE;
                wire BUFFER_WRITE;
 
 
                wire [7:0] TIME_OUT;
                wire [7:0] TIME_OUT;
                wire TICK_OUT;
                wire TICK_OUT;
 
 
                wire TOP_DOUT;
                wire TOP_DOUT;
                wire TOP_SOUT;
                wire TOP_SOUT;
 
 
                wire TOP_TX_READY;
                wire TOP_TX_READY;
                wire TOP_TX_READY_TICK;
                wire TOP_TX_READY_TICK;
 
 
                wire [5:0] TOP_FSM;
                wire [5:0] TOP_FSM;
 
 
                wire TX_CLOCK_RECOVERY_VLOG;
                wire TX_CLOCK_RECOVERY_VLOG;
                wire [3:0] SPW_SC_FSM;
                wire [3:0] SPW_SC_FSM;
                wire [3:0] SPW_SC_FSM_OUT;
                wire [3:0] SPW_SC_FSM_OUT;
 
 
                assign TX_CLOCK_RECOVERY_VLOG = TOP_DOUT ^ TOP_SOUT;
                assign TX_CLOCK_RECOVERY_VLOG = TOP_DOUT ^ TOP_SOUT;
                assign SPW_SC_FSM_OUT = SPW_SC_FSM;
                assign SPW_SC_FSM_OUT = SPW_SC_FSM;
 
 
                integer i;
                integer i;
 
 
                initial
                initial
                 begin
                 begin
                        $dumpfile("module_tb.vcd");
                        $dumpfile("module_tb.vcd");
                        $dumpvars(0,module_tb);
                        $dumpvars(0,module_tb);
                        $global_init;
                        $global_init;
                        i=0;
                        i=0;
 
                        time_clk_ns = 500;
                 end
                 end
 
 
                initial PCLK = 1'b0;
                initial PCLK = 1'b0;
                always #(5) PCLK = ~PCLK;
                always #(5) PCLK = ~PCLK;
 
 
                initial PPLLCLK = 1'b0;
                initial PPLLCLK = 1'b0;
                always #(100) PPLLCLK = ~PPLLCLK;
                always #(time_clk_ns/2) PPLLCLK = ~PPLLCLK;
 
 
                initial CLK_SIM = 1'b0;
                initial CLK_SIM = 1'b0;
                always #(1) CLK_SIM = ~CLK_SIM;
                always #(1) CLK_SIM = ~CLK_SIM;
 
 
 
 
                top_spw_ultra_light DUT_ULIGHT(
                top_spw_ultra_light DUT_ULIGHT(
                                        .pclk(PCLK),
                                        .pclk(PCLK),
                                        .ppllclk(PPLLCLK),
                                        .ppllclk(PPLLCLK),
                                        .resetn(RESETN),
                                        .resetn(RESETN),
 
 
                                        .top_sin(TOP_SIN),
                                        .top_sin(TOP_SIN),
                                        .top_din(TOP_DIN),
                                        .top_din(TOP_DIN),
 
 
                                        .top_auto_start(AUTO_START),
                                        .top_auto_start(AUTO_START),
                                        .top_link_start(LINK_START),
                                        .top_link_start(LINK_START),
                                        .top_link_disable(LINK_DISABLE),
                                        .top_link_disable(LINK_DISABLE),
 
 
                                        .top_tx_write(TOP_TX_WRITE),
                                        .top_tx_write(TOP_TX_WRITE),
                                        .top_tx_data(TOP_TX_DATA),
                                        .top_tx_data(TOP_TX_DATA),
 
 
                                        .top_tx_tick(TOP_TX_TICK),
                                        .top_tx_tick(TOP_TX_TICK),
                                        .top_tx_time(TOP_TX_TIME),
                                        .top_tx_time(TOP_TX_TIME),
 
 
                                        .credit_error_rx(CREDIT_ERROR_RX),
                                        .credit_error_rx(CREDIT_ERROR_RX),
                                        .top_send_fct_now(TOP_SEND_FCT_NOW),
                                        .top_send_fct_now(TOP_SEND_FCT_NOW),
 
 
                                        .datarx_flag(DATARX_FLAG),
                                        .datarx_flag(DATARX_FLAG),
                                        .buffer_write(BUFFER_WRITE),
                                        .buffer_write(BUFFER_WRITE),
 
 
                                        .time_out(TIME_OUT),
                                        .time_out(TIME_OUT),
                                        .tick_out(TICK_OUT),
                                        .tick_out(TICK_OUT),
 
 
                                        .top_dout(TOP_DOUT),
                                        .top_dout(TOP_DOUT),
                                        .top_sout(TOP_SOUT),
                                        .top_sout(TOP_SOUT),
 
 
                                        .top_tx_ready(TOP_TX_READY),
                                        .top_tx_ready(TOP_TX_READY),
                                        .top_tx_ready_tick(TOP_TX_READY_TICK),
                                        .top_tx_ready_tick(TOP_TX_READY_TICK),
 
 
                                        .top_fsm(TOP_FSM)
                                        .top_fsm(TOP_FSM)
                                      );
                                      );
 
 
 
 
 
 
 
 
        //
        //
        always@(posedge PCLK)
        always@(posedge PCLK)
                $write_tx_fsm_spw_ultra_light;
                $write_tx_fsm_spw_ultra_light;
 
 
        //
        //
        always@(posedge PCLK)
        always@(posedge PCLK or posedge TOP_TX_READY)
                $write_tx_data_spw_ultra_light;
                $write_tx_data_spw_ultra_light;
 
 
        always@(posedge PCLK)
        always@(posedge PCLK)
                $write_tx_time_code_spw_ultra_light;
                $write_tx_time_code_spw_ultra_light;
 
 
        //
        //
        always@(posedge BUFFER_WRITE)
        always@(posedge BUFFER_WRITE)
                $receive_rx_data_spw_ultra_light;
                $receive_rx_data_spw_ultra_light;
 
 
        always@(posedge TICK_OUT)
        always@(posedge TICK_OUT)
                $receive_rx_time_code_spw_ultra_light;
                $receive_rx_time_code_spw_ultra_light;
 
 
        //
        //
        always@(posedge PCLK , negedge PCLK)
        always@(posedge PCLK , negedge PCLK)
                $global_reset;
                $global_reset;
 
 
        //
        //
        always@(posedge CLK_SIM)
        always@(posedge CLK_SIM)
                $run_sim;
                $run_sim;
 
 
        //FLAG USED TO FINISH SIMULATION PROGRAM 
        //FLAG USED TO FINISH SIMULATION PROGRAM 
        always@(posedge CLK_SIM)
        always@(posedge CLK_SIM)
        begin
        begin
                wait(i == 1);
                wait(i == 1);
                $finish();
                $finish();
        end
        end
 
 
 
 
endmodule
endmodule
 
 

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