`timescale 1ns/1ns
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`timescale 1ns/1ns
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`default_nettype none
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`default_nettype none
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module module_tb;
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module module_tb;
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reg CLK_SIM;
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reg CLK_SIM;
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`ifdef VERILOG_A
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`ifdef VERILOG_A
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/*SPWTCR*/
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/*SPWTCR*/
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wire CLOCK;
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wire CLOCK;
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reg CLK;
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reg CLK;
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wire RESETn;
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wire RESETn;
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wire LINK_START;
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wire LINK_START;
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wire LINK_DISABLE;
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wire LINK_DISABLE;
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wire AUTOSTART;
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wire AUTOSTART;
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wire [2:0] CURRENTSTATE;
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wire [2:0] CURRENTSTATE;
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wire [10:0] FLAGS;
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wire [10:0] FLAGS;
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wire [8:0] DATA_I;
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wire [8:0] DATA_I;
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wire WR_DATA;
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wire WR_DATA;
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wire TX_FULL;
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wire TX_FULL;
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wire [8:0] DATA_O;
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wire [8:0] DATA_O;
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wire RD_DATA;
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wire RD_DATA;
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wire RX_EMPTY;
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wire RX_EMPTY;
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wire TICK_OUT;
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wire TICK_OUT;
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wire [7:0] TIME_OUT;
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wire [7:0] TIME_OUT;
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wire TICK_IN;
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wire TICK_IN;
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wire [7:0] TIME_IN;
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wire [7:0] TIME_IN;
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wire [6:0] TX_CLK_DIV;
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wire [6:0] TX_CLK_DIV;
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wire SPILL_ENABLE;
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wire SPILL_ENABLE;
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wire Din;
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wire Din;
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wire Sin;
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wire Sin;
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wire Dout;
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wire Dout;
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wire Sout;
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wire Sout;
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wire [3:0] SPW_SC_FSM;
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wire [3:0] SPW_SC_FSM;
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wire [3:0] SPW_SC_FSM_OUT;
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wire [3:0] SPW_SC_FSM_OUT;
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wire RX_CLOCK_RECOVERY_SC;
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wire RX_CLOCK_RECOVERY_SC;
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wire TX_CLOCK_RECOVERY_VLOG;
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wire TX_CLOCK_RECOVERY_VLOG;
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wire TX_CLOCK_OUT;
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wire TX_CLOCK_OUT;
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wire TX_CLOCK_OUT_SC;
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wire TX_CLOCK_OUT_SC;
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assign RX_CLOCK_RECOVERY_SC = Din ^ Sin;
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assign RX_CLOCK_RECOVERY_SC = Din ^ Sin;
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assign TX_CLOCK_OUT_SC = TX_CLOCK_OUT;
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assign TX_CLOCK_OUT_SC = TX_CLOCK_OUT;
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assign SPW_SC_FSM_OUT = SPW_SC_FSM;
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assign SPW_SC_FSM_OUT = SPW_SC_FSM;
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assign TX_CLOCK_RECOVERY_VLOG = Dout ^ Sout;
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assign TX_CLOCK_RECOVERY_VLOG = Dout ^ Sout;
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assign CLOCK = CLK;
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assign CLOCK = CLK;
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initial CLK = 1'b0;
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initial CLK = 1'b0;
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always #(10) CLK = ~CLK;
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always #(10) CLK = ~CLK;
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SpwTCR DUT_TCR (
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SpwTCR DUT_TCR (
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.CLOCK(CLOCK),
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.CLOCK(CLOCK),
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.RESETn(RESETn),
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.RESETn(RESETn),
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.LINK_START(LINK_START),
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.LINK_START(LINK_START),
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.LINK_DISABLE(LINK_DISABLE),
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.LINK_DISABLE(LINK_DISABLE),
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.AUTOSTART(AUTOSTART),
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.AUTOSTART(AUTOSTART),
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.CURRENTSTATE(CURRENTSTATE),
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.CURRENTSTATE(CURRENTSTATE),
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.FLAGS(FLAGS),
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.FLAGS(FLAGS),
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.DATA_I(DATA_I),
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.DATA_I(DATA_I),
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.WR_DATA(WR_DATA),
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.WR_DATA(WR_DATA),
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.TX_FULL(TX_FULL),
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.TX_FULL(TX_FULL),
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.DATA_O(DATA_O),
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.DATA_O(DATA_O),
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.RD_DATA(RD_DATA),
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.RD_DATA(RD_DATA),
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.RX_EMPTY(RX_EMPTY),
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.RX_EMPTY(RX_EMPTY),
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.TICK_OUT(TICK_OUT),
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.TICK_OUT(TICK_OUT),
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.TIME_OUT(TIME_OUT),
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.TIME_OUT(TIME_OUT),
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.TICK_IN(TICK_IN),
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.TICK_IN(TICK_IN),
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.TIME_IN(TIME_IN),
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.TIME_IN(TIME_IN),
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.TX_CLK_DIV(TX_CLK_DIV),
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.TX_CLK_DIV(TX_CLK_DIV),
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.SPILL_ENABLE(SPILL_ENABLE),
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.SPILL_ENABLE(SPILL_ENABLE),
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.Din(Din),
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.Din(Din),
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.Sin(Sin),
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.Sin(Sin),
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.Dout(Dout),
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.Dout(Dout),
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.Sout(Sout)
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.Sout(Sout)
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);
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);
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always@(posedge CLK , negedge CLK)
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always@(posedge CLK , negedge CLK)
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$global_reset;
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$global_reset;
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always@(posedge CLK)
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always@(posedge CLK)
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$write_tx_spw;
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$write_tx_spw;
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always@(posedge CLK)
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always@(posedge CLK)
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$receive_rx_spw;
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$receive_rx_spw;
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//FLAG USED TO FINISH SIMULATION PROGRAM
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//FLAG USED TO FINISH SIMULATION PROGRAM
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always@(posedge CLK)
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always@(posedge CLK)
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begin
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begin
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wait(i == 1);
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wait(i == 1);
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$finish();
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$finish();
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end
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end
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`endif
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`endif
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`ifdef VERILOG_B
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`ifdef VERILOG_B
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`endif
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`endif
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integer time_clk_ns;
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integer time_clk_ns;
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reg PCLK;
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reg PCLK;
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reg PPLLCLK;
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reg PPLLCLK;
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wire RESETN;
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wire RESETN;
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wire TOP_SIN;
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wire TOP_SIN;
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wire TOP_DIN;
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wire TOP_DIN;
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wire AUTO_START;
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wire AUTO_START;
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wire LINK_START;
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wire LINK_START;
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wire LINK_DISABLE;
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wire LINK_DISABLE;
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wire TOP_TX_WRITE;
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wire TOP_TX_WRITE;
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wire [8:0] TOP_TX_DATA;
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wire [8:0] TOP_TX_DATA;
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wire TOP_TX_TICK;
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wire TOP_TX_TICK;
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wire [7:0] TOP_TX_TIME;
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wire [7:0] TOP_TX_TIME;
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wire CREDIT_ERROR_RX;
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wire CREDIT_ERROR_RX;
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wire TOP_SEND_FCT_NOW;
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wire TOP_SEND_FCT_NOW;
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wire [8:0] DATARX_FLAG;
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wire [8:0] DATARX_FLAG;
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wire BUFFER_WRITE;
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wire BUFFER_WRITE;
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wire [7:0] TIME_OUT;
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wire [7:0] TIME_OUT;
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wire TICK_OUT;
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wire TICK_OUT;
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wire TOP_DOUT;
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wire TOP_DOUT;
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wire TOP_SOUT;
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wire TOP_SOUT;
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wire TOP_TX_READY;
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wire TOP_TX_READY;
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wire TOP_TX_READY_TICK;
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wire TOP_TX_READY_TICK;
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wire [5:0] TOP_FSM;
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wire [5:0] TOP_FSM;
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wire TX_CLOCK_RECOVERY_VLOG;
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wire TX_CLOCK_RECOVERY_VLOG;
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wire [3:0] SPW_SC_FSM;
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wire [3:0] SPW_SC_FSM;
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wire [3:0] SPW_SC_FSM_OUT;
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wire [3:0] SPW_SC_FSM_OUT;
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assign TX_CLOCK_RECOVERY_VLOG = TOP_DOUT ^ TOP_SOUT;
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assign TX_CLOCK_RECOVERY_VLOG = TOP_DOUT ^ TOP_SOUT;
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assign SPW_SC_FSM_OUT = SPW_SC_FSM;
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assign SPW_SC_FSM_OUT = SPW_SC_FSM;
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integer i;
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integer i;
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initial
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initial
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begin
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begin
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$dumpfile("module_tb.vcd");
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$dumpfile("module_tb.vcd");
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$dumpvars(0,module_tb);
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$dumpvars(0,module_tb);
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$global_init;
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$global_init;
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i=0;
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i=0;
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time_clk_ns = 500;
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end
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end
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initial PCLK = 1'b0;
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initial PCLK = 1'b0;
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always #(5) PCLK = ~PCLK;
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always #(5) PCLK = ~PCLK;
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initial PPLLCLK = 1'b0;
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initial PPLLCLK = 1'b0;
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always #(100) PPLLCLK = ~PPLLCLK;
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always #(time_clk_ns/2) PPLLCLK = ~PPLLCLK;
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initial CLK_SIM = 1'b0;
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initial CLK_SIM = 1'b0;
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always #(1) CLK_SIM = ~CLK_SIM;
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always #(1) CLK_SIM = ~CLK_SIM;
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top_spw_ultra_light DUT_ULIGHT(
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top_spw_ultra_light DUT_ULIGHT(
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.pclk(PCLK),
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.pclk(PCLK),
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.ppllclk(PPLLCLK),
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.ppllclk(PPLLCLK),
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.resetn(RESETN),
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.resetn(RESETN),
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.top_sin(TOP_SIN),
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.top_sin(TOP_SIN),
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.top_din(TOP_DIN),
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.top_din(TOP_DIN),
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.top_auto_start(AUTO_START),
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.top_auto_start(AUTO_START),
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.top_link_start(LINK_START),
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.top_link_start(LINK_START),
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.top_link_disable(LINK_DISABLE),
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.top_link_disable(LINK_DISABLE),
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.top_tx_write(TOP_TX_WRITE),
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.top_tx_write(TOP_TX_WRITE),
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.top_tx_data(TOP_TX_DATA),
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.top_tx_data(TOP_TX_DATA),
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.top_tx_tick(TOP_TX_TICK),
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.top_tx_tick(TOP_TX_TICK),
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.top_tx_time(TOP_TX_TIME),
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.top_tx_time(TOP_TX_TIME),
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.credit_error_rx(CREDIT_ERROR_RX),
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.credit_error_rx(CREDIT_ERROR_RX),
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.top_send_fct_now(TOP_SEND_FCT_NOW),
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.top_send_fct_now(TOP_SEND_FCT_NOW),
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.datarx_flag(DATARX_FLAG),
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.datarx_flag(DATARX_FLAG),
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.buffer_write(BUFFER_WRITE),
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.buffer_write(BUFFER_WRITE),
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.time_out(TIME_OUT),
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.time_out(TIME_OUT),
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.tick_out(TICK_OUT),
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.tick_out(TICK_OUT),
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.top_dout(TOP_DOUT),
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.top_dout(TOP_DOUT),
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.top_sout(TOP_SOUT),
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.top_sout(TOP_SOUT),
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.top_tx_ready(TOP_TX_READY),
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.top_tx_ready(TOP_TX_READY),
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.top_tx_ready_tick(TOP_TX_READY_TICK),
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.top_tx_ready_tick(TOP_TX_READY_TICK),
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.top_fsm(TOP_FSM)
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.top_fsm(TOP_FSM)
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);
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);
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//
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//
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always@(posedge PCLK)
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always@(posedge PCLK)
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$write_tx_fsm_spw_ultra_light;
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$write_tx_fsm_spw_ultra_light;
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//
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//
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always@(posedge PCLK)
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always@(posedge PCLK or posedge TOP_TX_READY)
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$write_tx_data_spw_ultra_light;
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$write_tx_data_spw_ultra_light;
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always@(posedge PCLK)
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always@(posedge PCLK)
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$write_tx_time_code_spw_ultra_light;
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$write_tx_time_code_spw_ultra_light;
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//
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//
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always@(posedge BUFFER_WRITE)
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always@(posedge BUFFER_WRITE)
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$receive_rx_data_spw_ultra_light;
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$receive_rx_data_spw_ultra_light;
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always@(posedge TICK_OUT)
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always@(posedge TICK_OUT)
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$receive_rx_time_code_spw_ultra_light;
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$receive_rx_time_code_spw_ultra_light;
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//
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//
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always@(posedge PCLK , negedge PCLK)
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always@(posedge PCLK , negedge PCLK)
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$global_reset;
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$global_reset;
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//
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//
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always@(posedge CLK_SIM)
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always@(posedge CLK_SIM)
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$run_sim;
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$run_sim;
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//FLAG USED TO FINISH SIMULATION PROGRAM
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//FLAG USED TO FINISH SIMULATION PROGRAM
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always@(posedge CLK_SIM)
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always@(posedge CLK_SIM)
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begin
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begin
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wait(i == 1);
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wait(i == 1);
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$finish();
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$finish();
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end
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end
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endmodule
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endmodule
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