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https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
[/] [spacewiresystemc/] [trunk/] [work/] [SpaceWrireTestSuit.glade] - Diff between revs 5 and 9
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Rev 9 |
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True
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vertical
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vertical
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True
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center
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center
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center
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center
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11
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31
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center
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center
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Link Enable
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Link Enable
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True
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False
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Auto Start
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Auto Start
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True
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False
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False
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1
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Link Disable
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Link Disable
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True
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False
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2
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2
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Set Flag
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Set Flag
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True
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True
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True
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True
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True
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True
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True
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True
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3
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3
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True
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Verilog Interface
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Verilog Interface
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True
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True
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True
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7
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True
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True
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False
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center
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center
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center
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center
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False
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center
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center
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True
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False
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False
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Enter Frequency
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Enter Frequency
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True
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True
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1
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1
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Set Frequency
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Set Frequency
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True
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True
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True
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True
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True
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True
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True
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True
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True
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True
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3
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3
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True
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True
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False
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False
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SystemC Tx frequency
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SystemC Tx frequency
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True
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True
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True
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True
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7
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7
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1
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1
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True
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True
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False
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center
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center
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center
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center
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8
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8
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11
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0
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none
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none
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True
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True
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False
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True
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True
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False
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False
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31
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center
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center
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Link Disable
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Link Disable
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True
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True
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True
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True
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True
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True
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True
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True
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True
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True
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0
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0
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Link Enable
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Link Enable
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True
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True
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True
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True
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True
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True
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True
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True
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True
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True
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1
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1
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Auto Start
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Auto Start
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True
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True
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True
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True
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True
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True
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True
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True
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True
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True
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2
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2
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Reset
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Reset
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True
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True
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True
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True
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True
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True
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True
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True
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True
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True
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3
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3
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Finish Simulation
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Finish Simulation
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True
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True
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True
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True
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True
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True
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True
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True
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True
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True
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4
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4
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True
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True
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False
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False
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Verilog Interface
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Verilog Interface
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True
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True
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True
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True
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7
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7
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2
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2
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True
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True
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False
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False
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center
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center
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center
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center
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11
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11
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12
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0
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0
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none
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none
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True
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True
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False
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False
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12
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12
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True
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True
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False
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False
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31
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31
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center
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center
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True
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True
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False
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False
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True
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True
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True
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True
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0
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0
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True
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True
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False
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False
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True
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True
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True
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True
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7
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7
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3
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3
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True
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True
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False
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False
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Basic Configuration
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Basic Configuration
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False
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False
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True
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True
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False
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False
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vertical
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vertical
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True
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False
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center
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center
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11
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12
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0
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none
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True
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False
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12
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True
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False
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31
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center
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Eop
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True
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True
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False
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True
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True
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True
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0
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Eep
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True
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True
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False
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True
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True
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True
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1
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Time Code
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True
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True
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False
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True
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True
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True
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2
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Generate
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True
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True
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True
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True
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True
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3
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True
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False
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Data Generation Verilog
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True
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True
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7
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0
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True
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True
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False
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False
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center
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center
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center
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center
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11
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11
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12
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12
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0
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0
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none
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none
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True
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True
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False
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False
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12
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12
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True
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True
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False
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False
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31
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31
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center
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center
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Eop Test
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Eop Test
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True
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True
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True
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True
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False
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False
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True
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True
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True
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True
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True
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True
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0
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0
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Eep Test
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Eep Test
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True
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True
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True
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True
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False
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False
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True
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True
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True
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True
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True
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True
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1
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1
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Time Code Test
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Time Code Test
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True
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True
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True
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True
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False
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False
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True
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True
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True
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True
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True
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True
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2
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2
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Start Test
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Start Test
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True
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True
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True
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True
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True
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True
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True
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True
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True
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True
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3
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3
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True
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True
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False
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False
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Verilog Interface
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Verilog Interface
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True
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True
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True
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True
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7
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7
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1
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1
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1
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1
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True
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True
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False
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False
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Data Verilog Test Suit
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Data Verilog Test Suit
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1
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1
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False
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False
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True
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True
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False
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False
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vertical
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vertical
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True
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True
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False
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False
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center
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center
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center
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center
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20
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20
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20
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20
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11
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11
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12
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12
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0
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0
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none
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none
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True
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True
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False
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False
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12
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12
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True
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True
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False
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False
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31
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31
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center
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center
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Send Data
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Send Data
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True
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True
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True
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True
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True
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True
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True
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True
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True
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True
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0
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0
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Enable Time Code
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Enable Time Code
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True
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True
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True
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True
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True
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True
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True
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True
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True
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True
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3
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3
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True
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True
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False
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False
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Verilog Interface
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Verilog Interface
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True
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True
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True
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True
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7
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7
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1
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1
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2
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2
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True
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True
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False
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False
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Data SystemC Test Suit
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Data SystemC Test Suit
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2
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2
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False
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False
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