module l1dir(
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module l1dir(
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input clk,
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input clk,
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input reset,
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input reset,
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input cpu, // Issuing CPU number
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input cpu, // Issuing CPU number
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input strobe, // Start transaction
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input strobe, // Start transaction
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input [ 1:0] way, // Way to allocate for allocating loads
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input [ 1:0] way, // Way to allocate for allocating loads
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input [39:0] address,
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input [39:0] address,
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input load,
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input load,
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input ifill,
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input ifill,
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input store,
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input store,
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input cas,
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input cas,
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input swap,
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input swap,
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input strload,
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input strload,
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input strstore,
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input strstore,
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input cacheable,
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input cacheable,
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input prefetch,
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input prefetch,
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input invalidate,
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input invalidate,
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input blockstore,
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input blockstore,
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output [111:0] inval_vect0, // Invalidation vector
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output [111:0] inval_vect0, // Invalidation vector
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output [111:0] inval_vect1,
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output [111:0] inval_vect1,
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output [ 1:0] othercachehit, // Other cache hit in the same CPU, wayval0/wayval1
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output [ 1:0] othercachehit, // Other cache hit in the same CPU, wayval0/wayval1
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output [ 1:0] othercpuhit, // Any cache hit in the other CPU, wayval0/wayval1
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output [ 1:0] othercpuhit, // Any cache hit in the other CPU, wayval0/wayval1
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output [ 1:0] wayval0, // Way valid
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output [ 1:0] wayval0, // Way valid
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output [ 1:0] wayval1, // Second way valid for ifill
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output [ 1:0] wayval1, // Second way valid for ifill
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output ready // Directory init done
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output ready // Directory init done
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);
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);
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wire [3:0] rdy;
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wire [3:0] rdy;
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wire dquery0=(!cpu) && store && (!blockstore);
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wire dquery0=(!cpu) && store && (!blockstore);
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wire dquery1= cpu && store && (!blockstore);
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wire dquery1= cpu && store && (!blockstore);
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wire dalloc0=(!cpu) && cacheable && (!invalidate) && load && (!prefetch);
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wire dalloc0=(!cpu) && cacheable && (!invalidate) && load && (!prefetch);
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wire dalloc1= cpu && cacheable && (!invalidate) && load && (!prefetch);
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wire dalloc1= cpu && cacheable && (!invalidate) && load && (!prefetch);
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wire ddealloc0=((!cpu) && ((ifill && (!prefetch) && (!invalidate)) || cas || swap || strstore || (store && blockstore))) ||
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wire ddealloc0=((!cpu) && ((ifill && (!prefetch) && (!invalidate)) || cas || swap || strstore || (store && blockstore))) ||
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( cpu && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
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( cpu && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
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wire ddealloc1=( cpu && ((ifill && (!prefetch) && (!invalidate)) || cas || swap || strstore || (store && blockstore))) ||
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wire ddealloc1=( cpu && ((ifill && (!prefetch) && (!invalidate)) || cas || swap || strstore || (store && blockstore))) ||
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((!cpu) && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
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((!cpu) && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
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wire iquery0=0;
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wire iquery0=0;
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wire iquery1=0;
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wire iquery1=0;
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wire ialloc0=(!cpu) && cacheable && (!invalidate) && ifill;
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wire ialloc0=(!cpu) && cacheable && (!invalidate) && ifill;
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wire ialloc1= cpu && cacheable && (!invalidate) && ifill;
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wire ialloc1= cpu && cacheable && (!invalidate) && ifill;
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wire idealloc0=((!cpu) && ((load && cacheable && (!prefetch) && (!invalidate)) || store || cas || swap || strstore)) ||
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wire idealloc0=((!cpu) && ((load && cacheable && (!prefetch) && (!invalidate)) || store || cas || swap || strstore)) ||
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( cpu && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
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( cpu && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
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wire idealloc1=( cpu && ((load && cacheable && (!prefetch) && (!invalidate)) || store || cas || swap || strstore )) ||
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wire idealloc1=( cpu && ((load && cacheable && (!prefetch) && (!invalidate)) || store || cas || swap || strstore )) ||
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((!cpu) && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
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((!cpu) && ((load && cacheable && (!prefetch) && (!invalidate)) || (ifill && (!prefetch) && (!invalidate)) || store || cas || swap || strload || strstore));
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wire [2:0] cpu0_dhit0;
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wire [2:0] cpu0_dhit0;
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wire [2:0] cpu0_dhit1;
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wire [2:0] cpu0_dhit1;
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wire [2:0] cpu1_dhit0;
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wire [2:0] cpu1_dhit0;
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wire [2:0] cpu1_dhit1;
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wire [2:0] cpu1_dhit1;
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wire [2:0] cpu0_ihit;
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wire [2:0] cpu0_ihit;
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wire [2:0] cpu1_ihit;
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wire [2:0] cpu1_ihit;
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wire invalidate_d=invalidate && load;
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wire invalidate_d=invalidate && load;
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wire invalidate_i=invalidate && ifill;
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wire invalidate_i=invalidate && ifill;
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reg ifill_d;
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reg ifill_d;
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reg load_d;
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reg load_d;
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reg cacheable_d;
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reg cacheable_d;
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reg cpu_d;
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reg cpu_d;
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reg [39:0] address_d;
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reg [39:0] address_d;
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reg strobe_d;
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reg strobe_d;
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reg strobe_d1;
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reg strobe_d1;
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reg strobe_d2;
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reg strobe_d2;
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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strobe_d<=strobe;
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strobe_d<=strobe;
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strobe_d1<=strobe_d;
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strobe_d1<=strobe_d;
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strobe_d2<=strobe_d1;
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strobe_d2<=strobe_d1;
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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if(strobe)
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if(strobe)
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begin
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begin
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ifill_d<=ifill;
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ifill_d<=ifill;
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load_d<=load;
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load_d<=load;
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cacheable_d<=cacheable;
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cacheable_d<=cacheable;
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cpu_d<=cpu;
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cpu_d<=cpu;
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address_d<=address;
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address_d<=address;
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end
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end
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l1ddir cpu0_ddir(
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l1ddir cpu0_ddir(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.index(address[10:4]),
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.index(address[10:4]),
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.way(way),
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.way(way),
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.tag(address[39:11]),
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.tag(address[39:11]),
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.strobe(strobe),
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.strobe(strobe),
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.query(dquery0),
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.query(dquery0),
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.allocate(dalloc0),
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.allocate(dalloc0),
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.deallocate(ddealloc0),
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.deallocate(ddealloc0),
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.dualdealloc(ifill),
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.dualdealloc(ifill),
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.invalidate(invalidate_d && !cpu),
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.invalidate(invalidate_d && !cpu),
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.hit0(cpu0_dhit0),
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.hit0(cpu0_dhit0),
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.hit1(cpu0_dhit1),
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.hit1(cpu0_dhit1),
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.ready(rdy[0])
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.ready(rdy[0])
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);
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);
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l1ddir cpu1_ddir(
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l1ddir cpu1_ddir(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.index(address[10:4]),
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.index(address[10:4]),
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.way(way),
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.way(way),
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.tag(address[39:11]),
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.tag(address[39:11]),
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.strobe(strobe),
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.strobe(strobe),
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.query(dquery1),
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.query(dquery1),
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.allocate(dalloc1),
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.allocate(dalloc1),
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.deallocate(ddealloc1),
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.deallocate(ddealloc1),
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.dualdealloc(ifill),
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.dualdealloc(ifill),
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.invalidate(invalidate_d && cpu),
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.invalidate(invalidate_d && cpu),
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.hit0(cpu1_dhit0),
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.hit0(cpu1_dhit0),
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.hit1(cpu1_dhit1),
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.hit1(cpu1_dhit1),
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.ready(rdy[1])
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.ready(rdy[1])
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);
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);
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l1idir cpu0_idir(
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l1idir cpu0_idir(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.index(address[11:5]),
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.index(address[11:5]),
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.way(way),
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.way(way),
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.tag(address[39:12]),
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.tag(address[39:12]),
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.strobe(strobe),
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.strobe(strobe),
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.query(iquery0),
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.query(iquery0),
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.allocate(ialloc0),
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.allocate(ialloc0),
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.deallocate(idealloc0),
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.deallocate(idealloc0),
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.invalidate(invalidate_i && !cpu),
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.invalidate(invalidate_i && !cpu),
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.hit(cpu0_ihit),
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.hit(cpu0_ihit),
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.ready(rdy[2])
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.ready(rdy[2])
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);
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);
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l1idir cpu1_idir(
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l1idir cpu1_idir(
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.index(address[11:5]),
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.index(address[11:5]),
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.way(way),
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.way(way),
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.tag(address[39:12]),
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.tag(address[39:12]),
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.strobe(strobe),
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.strobe(strobe),
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.query(iquery1),
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.query(iquery1),
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.allocate(ialloc1),
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.allocate(ialloc1),
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.deallocate(idealloc1),
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.deallocate(idealloc1),
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.invalidate(invalidate_i && cpu),
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.invalidate(invalidate_i && cpu),
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.hit(cpu1_ihit),
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.hit(cpu1_ihit),
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.ready(rdy[3])
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.ready(rdy[3])
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);
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);
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assign ready=(!rdy[0] | !rdy[1] | !rdy[2] | !rdy[3]) ? 0:1;
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assign ready=(!rdy[0] | !rdy[1] | !rdy[2] | !rdy[3]) ? 0:1;
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assign inval_vect0[3:0]={wayval0,cpu0_ihit[2] && (!address_d[5]),cpu0_dhit0[2] && (address_d[5:4]==2'b00)};
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assign inval_vect0[3:0]={wayval0,cpu0_ihit[2] && (!address_d[5]),cpu0_dhit0[2] && (address_d[5:4]==2'b00)};
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assign inval_vect0[7:4]={wayval0,cpu1_ihit[2] && (!address_d[5]),cpu1_dhit0[2] && (address_d[5:4]==2'b00)};
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assign inval_vect0[7:4]={wayval0,cpu1_ihit[2] && (!address_d[5]),cpu1_dhit0[2] && (address_d[5:4]==2'b00)};
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assign inval_vect0[31:8]=0;
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assign inval_vect0[31:8]=0;
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assign inval_vect0[34:32]={wayval0,cpu0_dhit0[2] && (address_d[5:4]==2'b01)};
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assign inval_vect0[34:32]={wayval0,cpu0_dhit0[2] && (address_d[5:4]==2'b01)};
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assign inval_vect0[37:35]={wayval0,cpu1_dhit0[2] && (address_d[5:4]==2'b01)};
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assign inval_vect0[37:35]={wayval0,cpu1_dhit0[2] && (address_d[5:4]==2'b01)};
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assign inval_vect0[55:38]=0;
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assign inval_vect0[55:38]=0;
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assign inval_vect0[59:56]={wayval0,cpu0_ihit[2] && address_d[5],cpu0_dhit0[2] && (address_d[5:4]==2'b10)};
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assign inval_vect0[59:56]={wayval0,cpu0_ihit[2] && address_d[5],cpu0_dhit0[2] && (address_d[5:4]==2'b10)};
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assign inval_vect0[63:60]={wayval0,cpu1_ihit[2] && address_d[5],cpu1_dhit0[2] && (address_d[5:4]==2'b10)};
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assign inval_vect0[63:60]={wayval0,cpu1_ihit[2] && address_d[5],cpu1_dhit0[2] && (address_d[5:4]==2'b10)};
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assign inval_vect0[87:64]=0;
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assign inval_vect0[87:64]=0;
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assign inval_vect0[90:88]={wayval0,cpu0_dhit0[2] && (address_d[5:4]==2'b11)};
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assign inval_vect0[90:88]={wayval0,cpu0_dhit0[2] && (address_d[5:4]==2'b11)};
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assign inval_vect0[93:91]={wayval0,cpu1_dhit0[2] && (address_d[5:4]==2'b11)};
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assign inval_vect0[93:91]={wayval0,cpu1_dhit0[2] && (address_d[5:4]==2'b11)};
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assign inval_vect0[111:94]=0;
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assign inval_vect0[111:94]=0;
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|
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assign inval_vect1[3:0]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b00)};
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/*assign inval_vect1[3:0]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b00)};
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assign inval_vect1[7:4]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b00)};
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assign inval_vect1[7:4]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b00)};
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assign inval_vect1[31:8]=0;
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assign inval_vect1[34:32]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b01)};
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assign inval_vect1[37:35]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b01)};
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assign inval_vect1[55:38]=0;
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assign inval_vect1[59:56]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b10)};
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assign inval_vect1[63:60]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b10)};
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assign inval_vect1[87:64]=0;
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assign inval_vect1[90:88]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b11)};
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assign inval_vect1[93:91]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b11)};
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assign inval_vect1[111:94]=0;*/
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assign inval_vect1[3:0]=0;
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assign inval_vect1[7:4]=0;
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assign inval_vect1[31:8]=0;
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assign inval_vect1[31:8]=0;
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assign inval_vect1[34:32]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b01)};
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assign inval_vect1[34:32]={wayval1,cpu0_dhit1[2] && (address_d[5]==0)};
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assign inval_vect1[37:35]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b01)};
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assign inval_vect1[37:35]={wayval1,cpu1_dhit1[2] && (address_d[5]==0)};
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assign inval_vect1[55:38]=0;
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assign inval_vect1[55:38]=0;
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assign inval_vect1[59:56]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b10)};
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assign inval_vect1[59:56]=0;
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assign inval_vect1[63:60]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b10)};
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assign inval_vect1[63:60]=0;
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assign inval_vect1[87:64]=0;
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assign inval_vect1[87:64]=0;
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assign inval_vect1[90:88]={wayval1,cpu0_dhit1[2] && (address_d[5:4]==2'b11)};
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assign inval_vect1[90:88]={wayval1,cpu0_dhit1[2] && (address_d[5]==1)};
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assign inval_vect1[93:91]={wayval1,cpu1_dhit1[2] && (address_d[5:4]==2'b11)};
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assign inval_vect1[93:91]={wayval1,cpu1_dhit1[2] && (address_d[5]==1)};
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assign inval_vect1[111:94]=0;
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assign inval_vect1[111:94]=0;
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|
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assign wayval0=cpu0_dhit0[1:0] | cpu1_dhit0[1:0] | cpu0_ihit[1:0] | cpu1_ihit[1:0];
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assign wayval0=cpu0_dhit0[1:0] | cpu1_dhit0[1:0] | cpu0_ihit[1:0] | cpu1_ihit[1:0];
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assign wayval1=cpu0_dhit1[1:0] | cpu1_dhit1[1:0];
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assign wayval1=cpu0_dhit1[1:0] | cpu1_dhit1[1:0];
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assign othercachehit[0]=((!cpu_d) && ifill_d && cpu0_dhit0[2]) ||
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assign othercachehit[0]=((!cpu_d) && ifill_d && cpu0_dhit0[2]) ||
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( cpu_d && ifill_d && cpu1_dhit0[2]) ||
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( cpu_d && ifill_d && cpu1_dhit0[2]) ||
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((!cpu_d) && load_d && cacheable_d && cpu0_ihit[2]) ||
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((!cpu_d) && load_d && cacheable_d && cpu0_ihit[2]) ||
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( cpu_d && load_d && cacheable_d && cpu1_ihit[2]);
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( cpu_d && load_d && cacheable_d && cpu1_ihit[2]);
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assign othercachehit[1]=((!cpu_d) && ifill_d && cpu0_dhit1[2]) ||
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assign othercachehit[1]=((!cpu_d) && ifill_d && cpu0_dhit1[2]) ||
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( cpu_d && ifill_d && cpu1_dhit1[2]);
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( cpu_d && ifill_d && cpu1_dhit1[2]);
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assign othercpuhit[0]=((!cpu_d) && (cpu1_dhit0[2] || cpu1_ihit[2])) ||
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assign othercpuhit[0]=((!cpu_d) && (cpu1_dhit0[2] || cpu1_ihit[2])) ||
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( cpu_d && (cpu0_dhit0[2] || cpu0_ihit[2]));
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( cpu_d && (cpu0_dhit0[2] || cpu0_ihit[2]));
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assign othercpuhit[1]=((!cpu_d) && ifill_d && cpu1_dhit1[2]) ||
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assign othercpuhit[1]=((!cpu_d) && ifill_d && cpu1_dhit1[2]) ||
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( cpu_d && ifill_d && cpu0_dhit1[2]);
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( cpu_d && ifill_d && cpu0_dhit1[2]);
|
|
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wire [149:0] ILA_DATA;
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wire [149:0] ILA_DATA;
|
|
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st2 st2_inst(
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st2 st2_inst(
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.acq_clk(clk),
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.acq_clk(clk),
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.acq_data_in(ILA_DATA),
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.acq_data_in(ILA_DATA),
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.acq_trigger_in(ILA_DATA),
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.acq_trigger_in(ILA_DATA),
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.storage_enable(strobe || strobe_d || strobe_d1 || strobe_d2)
|
.storage_enable(strobe || strobe_d || strobe_d1 || strobe_d2)
|
);
|
);
|
|
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assign ILA_DATA[39:0]=address;
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assign ILA_DATA[39:0]=address;
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assign ILA_DATA[41:40]=way;
|
assign ILA_DATA[41:40]=way;
|
assign ILA_DATA[42]=strobe;
|
assign ILA_DATA[42]=strobe;
|
assign ILA_DATA[43]=load;
|
assign ILA_DATA[43]=load;
|
assign ILA_DATA[44]=ifill;
|
assign ILA_DATA[44]=ifill;
|
assign ILA_DATA[45]=store;
|
assign ILA_DATA[45]=store;
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assign ILA_DATA[46]=cas;
|
assign ILA_DATA[46]=cas;
|
assign ILA_DATA[47]=swap;
|
assign ILA_DATA[47]=swap;
|
assign ILA_DATA[48]=strload;
|
assign ILA_DATA[48]=strload;
|
assign ILA_DATA[49]=strstore;
|
assign ILA_DATA[49]=strstore;
|
assign ILA_DATA[50]=cacheable;
|
assign ILA_DATA[50]=cacheable;
|
assign ILA_DATA[51]=prefetch;
|
assign ILA_DATA[51]=prefetch;
|
assign ILA_DATA[52]=invalidate;
|
assign ILA_DATA[52]=invalidate;
|
assign ILA_DATA[53]=blockstore;
|
assign ILA_DATA[53]=blockstore;
|
assign ILA_DATA[55:54]=othercachehit;
|
assign ILA_DATA[55:54]=othercachehit;
|
assign ILA_DATA[57:56]=othercpuhit;
|
assign ILA_DATA[57:56]=othercpuhit;
|
assign ILA_DATA[59:58]=wayval0;
|
assign ILA_DATA[59:58]=wayval0;
|
assign ILA_DATA[61:60]=wayval1;
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assign ILA_DATA[61:60]=wayval1;
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assign ILA_DATA[69:62]=inval_vect0[7:0];
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assign ILA_DATA[69:62]=inval_vect0[7:0];
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assign ILA_DATA[75:70]=inval_vect0[37:32];
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assign ILA_DATA[75:70]=inval_vect0[37:32];
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assign ILA_DATA[83:76]=inval_vect0[63:56];
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assign ILA_DATA[83:76]=inval_vect0[63:56];
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assign ILA_DATA[89:84]=inval_vect0[93:88];
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assign ILA_DATA[89:84]=inval_vect0[93:88];
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assign ILA_DATA[97:90]=inval_vect1[7:0];
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assign ILA_DATA[97:90]=inval_vect1[7:0];
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assign ILA_DATA[103:98]=inval_vect1[37:32];
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assign ILA_DATA[103:98]=inval_vect1[37:32];
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assign ILA_DATA[111:104]=inval_vect1[63:56];
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assign ILA_DATA[111:104]=inval_vect1[63:56];
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assign ILA_DATA[117:112]=inval_vect1[93:88];
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assign ILA_DATA[117:112]=inval_vect1[93:88];
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assign ILA_DATA[118]=dquery0;
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assign ILA_DATA[118]=dquery0;
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assign ILA_DATA[119]=dquery1;
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assign ILA_DATA[119]=dquery1;
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assign ILA_DATA[120]=dalloc0;
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assign ILA_DATA[120]=dalloc0;
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assign ILA_DATA[121]=dalloc1;
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assign ILA_DATA[121]=dalloc1;
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assign ILA_DATA[122]=ddealloc0;
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assign ILA_DATA[122]=ddealloc0;
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assign ILA_DATA[123]=ddealloc1;
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assign ILA_DATA[123]=ddealloc1;
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assign ILA_DATA[124]=iquery0;
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assign ILA_DATA[124]=iquery0;
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assign ILA_DATA[125]=iquery1;
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assign ILA_DATA[125]=iquery1;
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assign ILA_DATA[126]=ialloc0;
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assign ILA_DATA[126]=ialloc0;
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assign ILA_DATA[127]=ialloc1;
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assign ILA_DATA[127]=ialloc1;
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assign ILA_DATA[128]=idealloc0;
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assign ILA_DATA[128]=idealloc0;
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assign ILA_DATA[129]=idealloc1;
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assign ILA_DATA[129]=idealloc1;
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|
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endmodule
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endmodule
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