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README for the spi_boot core
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README for the spi_boot core
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============================
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Version: $Date: 2005-02-20 13:39:06 $
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Version: $Date: 2005-02-20 13:39:06 $
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Description
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Description
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-----------
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The SD/MMC Bootloader is a CPLD design that manages configuration and
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The SD/MMC Bootloader is a CPLD design that manages configuration and
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bootstrapping of FPGAs. It is able to retrieve the required data from
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bootstrapping of FPGAs. It is able to retrieve the required data from
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SecureDigital (SD) cards or MultiMediaCards (MMC) and manages the FPGA
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SecureDigital (SD) cards or MultiMediaCards (MMC) and manages the FPGA
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configuration process. SD cards as well as MMCs are operated in SPI mode which
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configuration process. SD cards as well as MMCs are operated in SPI mode which
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is part of both standards thus eliminating the need for dedicated
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is part of both standards thus eliminating the need for dedicated
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implementations. The SD/MMC Bootloader fits both. Beyond configuration, this
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implementations. The SD/MMC Bootloader fits both. Beyond configuration, this
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core supports a bootstrapping strategy where multiple images are stored on one
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core supports a bootstrapping strategy where multiple images are stored on one
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single memory card.
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single memory card.
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For example consider a system completely based on SRAM. The bootloader
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For example consider a system completely based on SRAM. The bootloader
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provides an initial configuration data from the first image to the FPGA. This
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provides an initial configuration data from the first image to the FPGA. This
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image contains a design which pulls the next image from the memory card and
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image contains a design which pulls the next image from the memory card and
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transfers this data to SRAM. In the third step the final FPGA design is loaded
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transfers this data to SRAM. In the third step the final FPGA design is loaded
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from the third image.
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from the third image.
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The schematic (rev. A) shows how the core can be used with an FPGA board. I
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The schematic (rev. A) shows how the core can be used with an FPGA board. I
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use it to configure/boot the Xilinx Spartan IIe on BurchED's B5-X300
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use it to configure/boot the Xilinx Spartan IIe on BurchED's B5-X300
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board. SV2 fits the "SERIAL MODE" connector on this board but you will have to
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board. SV2 fits the "SERIAL MODE" connector on this board but you will have to
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add a separate wire from R6 to attach INIT. Please check the proper use of the
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add a separate wire from R6 to attach INIT. Please check the proper use of the
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pull-up resistors for your specific board.
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pull-up resistors for your specific board.
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Features
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Features
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--------
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--------
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* Configuration mode: configurates SRAM based FPGAs via slave serial mode
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* Configuration mode: configurates SRAM based FPGAs via slave serial mode
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(Xilinx and Altera)
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(Xilinx and Altera)
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* Data mode: provides stored data over a simple synchronous serial interface
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* Data mode: provides stored data over a simple synchronous serial interface
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* Broad compatability using SPI mode
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* Broad compatability using SPI mode
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+ SecureDigital cards using dedicated initialization command
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+ SecureDigital cards using dedicated initialization command
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+ MultiMediaCards (see below)
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+ MultiMediaCards (see below)
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* Operation triggerd by power-up or card insertion
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* Operation triggerd by power-up or card insertion
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Compatability
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Compatability
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These cards have been tested with the SD/MMC Bootloader:
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These cards have been tested with the SD/MMC Bootloader:
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* SanDisk 128 MB SD
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* SanDisk 128 MB SD
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* SanDisk 64 MB MMC
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* SanDisk 64 MB MMC
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* Panasonic 32 MB SD
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* Panasonic 32 MB SD
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Some MMC might fail with this core as not all cards support CMD18
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Some MMC might fail with this core as not all cards support CMD18
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(READ_MULTIPLE_BLOCK). Please consult the data sheet of your specific
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(READ_MULTIPLE_BLOCK). Please consult the data sheet of your specific
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model. In case your MMC does not implement CMD18 you might want to have a look
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model. In case your MMC does not implement CMD18 you might want to have a look
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at the FPGA MMC-Card Config project.
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at the FPGA MMC-Card Config project.
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Verification
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Verification
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The spi_boot core comes with a simple testbench that simulates an SD/MMC
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The spi_boot core comes with a simple testbench that simulates an SD/MMC
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card. All four implementations of the core are verified there in parallel
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card. All four implementations of the core are verified there in parallel
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while transferring the data for several sets.
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while transferring the data for several sets.
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You should normally not need to run the testbench. But in case you modified
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You should normally not need to run the testbench. But in case you modified
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the VHDL code the testbench gives some hints if the design has been broken.
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the VHDL code the testbench gives some hints if the design has been broken.
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Directory Structure
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Directory Structure
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-------------------
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-------------------
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The core's directory structure follows the proposal of OpenCores.org.
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The core's directory structure follows the proposal of OpenCores.org.
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spi_boot
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spi_boot
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\--+-- rtl
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\--+-- rtl
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| \-- vhdl : VHDL code containing the RTL description
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| \-- vhdl : VHDL code containing the RTL description
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| of the core.
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| of the core.
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+-- bench
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+-- bench
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| \-- vhdl : VHDL testbench code.
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| \-- vhdl : VHDL testbench code.
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\-- sim
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\-- sim
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\-- rtl_sim : Directory for running simulations.
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\-- rtl_sim : Directory for running simulations.
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RAM Loader
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RAM Loader
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Directory rtl/vhdl/ram_loader contains the sample design which loads the next
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Directory rtl/vhdl/ram_loader contains the sample design which loads the next
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image from the card and stores its contents to external asynchronous
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image from the card and stores its contents to external asynchronous
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RAM. After reading 64 KB it triggers a new configuration process for the final
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RAM. After reading 64 KB it triggers a new configuration process for the final
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FPGA design.
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FPGA design.
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Refer to the code for the mechanisms involved.
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Refer to the code for the mechanisms involved.
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Compiling the VHDL Code
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Compiling the VHDL Code
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-----------------------
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-----------------------
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VHDL compilation and simulation tasks take place inside in sim/rtl_sim
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VHDL compilation and simulation tasks take place inside in sim/rtl_sim
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directory. The project setup supports only the GHDL simulator (see
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directory. The project setup supports only the GHDL simulator (see
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http://ghdl.free.fr).
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http://ghdl.free.fr).
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To compile the code simply type at the shell
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To compile the code simply type at the shell
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$ make
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$ make
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This should result in a file called tb_behav_c0 which can be executed as any
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This should result in a file called tb_behav_c0 which can be executed as any
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other executable.
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other executable.
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The basic simple sequence list can be found in COMPILE_LIST. This can be
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The basic simple sequence list can be found in COMPILE_LIST. This can be
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useful to quickly set up the analyze stage of any compiler or
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useful to quickly set up the analyze stage of any compiler or
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synthesizer. Especially when synthesizing the code, you want to skip the VHDL
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synthesizer. Especially when synthesizing the code, you want to skip the VHDL
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configurations in *-c.vhd and everything below the bench/ directory.
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configurations in *-c.vhd and everything below the bench/ directory.
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References
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References
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* SanDisk SD Card Product Manual
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* SanDisk SD Card Product Manual
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http://www.sandisk.com/pdf/oem/ProdManualSDCardv1.9.pdf
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http://www.sandisk.com/pdf/oem/ProdManualSDCardv1.9.pdf
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* SanDisk MMC Product Manual
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* SanDisk MMC Product Manual
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http://www.sandisk.com/pdf/oem/manual-rs-mmcv1.0.pdf
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http://www.sandisk.com/pdf/oem/manual-rs-mmcv1.0.pdf
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* Toshiba SD Card Specification
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* Toshiba SD Card Specification
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http://i.cmpnet.com/chipcenter/memory/images/prod055.pdf
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http://i.cmpnet.com/chipcenter/memory/images/prod055.pdf
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* BurchED
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* BurchED
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http://burched.biz/
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http://burched.biz/
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* FPGA MMC-Card Config project
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* FPGA MMC-Card Config project
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http://www.opencores.org/projects.cgi/web/mmcfpgaconfig/overview
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http://www.opencores.org/projects.cgi/web/mmcfpgaconfig/overview
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