-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- SD/MMC Bootloader
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-- SD/MMC Bootloader
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-- Testbench
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-- Testbench
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--
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--
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-- $Id: tb.vhd,v 1.1 2005-02-08 21:09:20 arniml Exp $
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-- $Id: tb.vhd 77 2009-04-01 19:53:14Z arniml $
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--
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--
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-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved, see COPYING.
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-- All rights reserved, see COPYING.
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--
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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--
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- this list of conditions and the following disclaimer.
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--
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- documentation and/or other materials provided with the distribution.
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--
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--
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-- Neither the name of the author nor the names of other contributors may
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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-- specific prior written permission.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- Please report bugs to the author, but before you do so, please
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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-- you have the latest version of this file.
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--
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--
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-- The latest version of this file can be found at:
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
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-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity tb is
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entity tb is
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end tb;
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end tb;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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architecture behav of tb is
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architecture behav of tb is
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|
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component tb_elem
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component tb_elem
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generic (
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generic (
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chip_type_g : string := "none";
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chip_type_g : string := "none";
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has_sd_card_g : integer := 1
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has_sd_card_g : integer := 1
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);
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);
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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reset_i : in std_logic;
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reset_i : in std_logic;
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eos_o : out boolean
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eos_o : out boolean
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);
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);
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end component;
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end component;
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constant period_c : time := 100 ns;
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constant period_c : time := 100 ns;
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constant reset_level_c : integer := 0;
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constant reset_level_c : integer := 0;
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signal clk_s : std_logic;
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signal clk_s : std_logic;
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signal reset_s : std_logic;
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signal reset_s : std_logic;
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signal eos_full_s,
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signal eos_full_s,
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eos_mmc_s,
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eos_mmc_s,
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eos_sd_s,
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eos_sd_s,
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eos_minimal_s : boolean;
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eos_minimal_s : boolean;
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begin
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begin
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Testbench element including full featured chip
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-- Testbench element including full featured chip
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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tb_elem_full_b : tb_elem
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tb_elem_full_b : tb_elem
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generic map (
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generic map (
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chip_type_g => "Full Chip",
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chip_type_g => "Full Chip",
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has_sd_card_g => 1
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has_sd_card_g => 1
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)
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)
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port map (
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port map (
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clk_i => clk_s,
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clk_i => clk_s,
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reset_i => reset_s,
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reset_i => reset_s,
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eos_o => eos_full_s
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eos_o => eos_full_s
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);
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);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Testbench element including MMC chip
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-- Testbench element including MMC chip
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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tb_elem_mmc_b : tb_elem
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tb_elem_mmc_b : tb_elem
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generic map (
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generic map (
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chip_type_g => "MMC Chip",
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chip_type_g => "MMC Chip",
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has_sd_card_g => 0
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has_sd_card_g => 0
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)
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)
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port map (
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port map (
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clk_i => clk_s,
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clk_i => clk_s,
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reset_i => reset_s,
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reset_i => reset_s,
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eos_o => eos_mmc_s
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eos_o => eos_mmc_s
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);
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);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Testbench element including SD chip
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-- Testbench element including SD chip
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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tb_elem_sd_b : tb_elem
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tb_elem_sd_b : tb_elem
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generic map (
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generic map (
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chip_type_g => "SD Chip",
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chip_type_g => "SD Chip",
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has_sd_card_g => 1
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has_sd_card_g => 1
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)
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)
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port map (
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port map (
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clk_i => clk_s,
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clk_i => clk_s,
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reset_i => reset_s,
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reset_i => reset_s,
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eos_o => eos_sd_s
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eos_o => eos_sd_s
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);
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);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Testbench element including cip with minimal features
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-- Testbench element including cip with minimal features
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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tb_elem_minimal_b : tb_elem
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tb_elem_minimal_b : tb_elem
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generic map (
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generic map (
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chip_type_g => "Minimal Chip",
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chip_type_g => "Minimal Chip",
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has_sd_card_g => 0
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has_sd_card_g => 0
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)
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)
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port map (
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port map (
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clk_i => clk_s,
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clk_i => clk_s,
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reset_i => reset_s,
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reset_i => reset_s,
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eos_o => eos_minimal_s
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eos_o => eos_minimal_s
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);
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);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Clock Generator
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-- Clock Generator
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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clk: process
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clk: process
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begin
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begin
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clk_s <= '0';
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clk_s <= '0';
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wait for period_c / 2;
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wait for period_c / 2;
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clk_s <= '1';
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clk_s <= '1';
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wait for period_c / 2;
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wait for period_c / 2;
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end process clk;
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end process clk;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Reset Generator
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-- Reset Generator
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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reset: process
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reset: process
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begin
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begin
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if reset_level_c = 0 then
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if reset_level_c = 0 then
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reset_s <= '0';
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reset_s <= '0';
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else
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else
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reset_s <= '1';
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reset_s <= '1';
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end if;
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end if;
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wait for period_c * 4 + 10 ns;
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wait for period_c * 4 + 10 ns;
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reset_s <= not reset_s;
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reset_s <= not reset_s;
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wait;
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wait;
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end process reset;
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end process reset;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- End Of Simulation Detection
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-- End Of Simulation Detection
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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eos: process (eos_full_s,
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eos: process (eos_full_s,
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eos_mmc_s,
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eos_mmc_s,
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eos_sd_s,
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eos_sd_s,
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eos_minimal_s)
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eos_minimal_s)
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begin
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begin
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if eos_full_s and eos_mmc_s and eos_sd_s and eos_minimal_s then
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if eos_full_s and eos_mmc_s and eos_sd_s and eos_minimal_s then
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assert false
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assert false
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report "End of Simulation."
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report "End of Simulation."
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severity failure;
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severity failure;
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end if;
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end if;
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end process eos;
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end process eos;
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end behav;
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end behav;
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-------------------------------------------------------------------------------
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|
-- File History:
|
|
--
|
|
-- $Log: not supported by cvs2svn $
|
|
-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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