-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- SD/MMC Bootloader
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-- SD/MMC Bootloader
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-- Testbench for ram_loader
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-- Testbench for ram_loader
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--
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--
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-- $Id: tb_rl.vhd,v 1.1 2005-04-10 18:07:25 arniml Exp $
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-- $Id: tb_rl.vhd 77 2009-04-01 19:53:14Z arniml $
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--
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--
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-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved, see COPYING.
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-- All rights reserved, see COPYING.
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--
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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--
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- this list of conditions and the following disclaimer.
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--
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- documentation and/or other materials provided with the distribution.
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--
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--
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-- Neither the name of the author nor the names of other contributors may
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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-- specific prior written permission.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- Please report bugs to the author, but before you do so, please
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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-- you have the latest version of this file.
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--
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--
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-- The latest version of this file can be found at:
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
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-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity tb_rl is
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entity tb_rl is
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end tb_rl;
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end tb_rl;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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|
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architecture behav of tb_rl is
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architecture behav of tb_rl is
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component chip
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component chip
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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reset_i : in std_logic;
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reset_i : in std_logic;
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set_sel_n_i : in std_logic_vector(3 downto 0);
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set_sel_n_i : in std_logic_vector(3 downto 0);
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spi_clk_o : out std_logic;
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spi_clk_o : out std_logic;
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spi_cs_n_o : out std_logic;
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spi_cs_n_o : out std_logic;
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spi_data_in_i : in std_logic;
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spi_data_in_i : in std_logic;
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spi_data_out_o : out std_logic;
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spi_data_out_o : out std_logic;
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start_i : in std_logic;
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start_i : in std_logic;
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mode_i : in std_logic;
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mode_i : in std_logic;
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config_n_o : out std_logic;
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config_n_o : out std_logic;
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detached_o : out std_logic;
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detached_o : out std_logic;
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cfg_init_n_i : in std_logic;
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cfg_init_n_i : in std_logic;
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cfg_done_i : in std_logic;
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cfg_done_i : in std_logic;
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dat_done_i : in std_logic;
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dat_done_i : in std_logic;
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cfg_clk_o : out std_logic;
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cfg_clk_o : out std_logic;
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cfg_dat_o : out std_logic
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cfg_dat_o : out std_logic
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);
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);
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end component;
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end component;
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component card
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component card
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generic (
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generic (
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card_type_g : string := "none";
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card_type_g : string := "none";
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is_sd_card_g : integer := 1
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is_sd_card_g : integer := 1
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);
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);
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port (
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port (
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spi_clk_i : in std_logic;
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spi_clk_i : in std_logic;
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spi_cs_n_i : in std_logic;
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spi_cs_n_i : in std_logic;
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spi_data_i : in std_logic;
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spi_data_i : in std_logic;
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spi_data_o : out std_logic
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spi_data_o : out std_logic
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);
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);
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end component;
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end component;
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component ram_loader
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component ram_loader
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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reset_i : in std_logic;
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reset_i : in std_logic;
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lamp_o : out std_logic;
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lamp_o : out std_logic;
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cfg_clk_i : in std_logic;
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cfg_clk_i : in std_logic;
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cfg_data_i : in std_logic;
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cfg_data_i : in std_logic;
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start_o : out std_logic;
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start_o : out std_logic;
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mode_o : out std_logic;
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mode_o : out std_logic;
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done_o : out std_logic;
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done_o : out std_logic;
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detached_i : in std_logic;
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detached_i : in std_logic;
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ram_addr_o : out std_logic_vector(15 downto 0);
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ram_addr_o : out std_logic_vector(15 downto 0);
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ram_data_b : out std_logic_vector( 7 downto 0);
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ram_data_b : out std_logic_vector( 7 downto 0);
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ram_ce_no : out std_logic_vector( 3 downto 0);
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ram_ce_no : out std_logic_vector( 3 downto 0);
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ram_oe_no : out std_logic;
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ram_oe_no : out std_logic;
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ram_we_no : out std_logic
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ram_we_no : out std_logic
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);
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);
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end component;
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end component;
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constant period_c : time := 100 ns;
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constant period_c : time := 100 ns;
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constant rl_period_c : time := 20 ns;
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constant rl_period_c : time := 20 ns;
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constant reset_level_c : integer := 0;
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constant reset_level_c : integer := 0;
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signal clk_s : std_logic;
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signal clk_s : std_logic;
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signal rl_clk_s: std_logic;
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signal rl_clk_s: std_logic;
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signal reset_s : std_logic;
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signal reset_s : std_logic;
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-- SPI interface signals
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-- SPI interface signals
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signal spi_clk_s : std_logic;
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signal spi_clk_s : std_logic;
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signal spi_data_to_card_s : std_logic;
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signal spi_data_to_card_s : std_logic;
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signal spi_data_from_card_s : std_logic;
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signal spi_data_from_card_s : std_logic;
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signal spi_cs_n_s : std_logic;
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signal spi_cs_n_s : std_logic;
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-- config related signals
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-- config related signals
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signal start_s : std_logic;
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signal start_s : std_logic;
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signal mode_s : std_logic;
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signal mode_s : std_logic;
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signal config_n_s : std_logic;
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signal config_n_s : std_logic;
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signal cfg_init_n_s : std_logic;
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signal cfg_init_n_s : std_logic;
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signal cfg_done_s : std_logic;
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signal cfg_done_s : std_logic;
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signal dat_done_s : std_logic;
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signal dat_done_s : std_logic;
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signal cfg_clk_s : std_logic;
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signal cfg_clk_s : std_logic;
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signal cfg_dat_s : std_logic;
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signal cfg_dat_s : std_logic;
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signal detached_s : std_logic;
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signal detached_s : std_logic;
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signal set_sel_n_s : std_logic_vector(3 downto 0);
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signal set_sel_n_s : std_logic_vector(3 downto 0);
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begin
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begin
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set_sel_n_s <= (others => '1');
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set_sel_n_s <= (others => '1');
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cfg_init_n_s <= '1';
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cfg_init_n_s <= '1';
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cfg_done_s <= '1';
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cfg_done_s <= '1';
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- DUT
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-- DUT
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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dut_b : chip
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dut_b : chip
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port map (
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port map (
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clk_i => clk_s,
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clk_i => clk_s,
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reset_i => reset_s,
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reset_i => reset_s,
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set_sel_n_i => set_sel_n_s,
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set_sel_n_i => set_sel_n_s,
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spi_clk_o => spi_clk_s,
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spi_clk_o => spi_clk_s,
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spi_cs_n_o => spi_cs_n_s,
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spi_cs_n_o => spi_cs_n_s,
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spi_data_in_i => spi_data_from_card_s,
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spi_data_in_i => spi_data_from_card_s,
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spi_data_out_o => spi_data_to_card_s,
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spi_data_out_o => spi_data_to_card_s,
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start_i => start_s,
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start_i => start_s,
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mode_i => mode_s,
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mode_i => mode_s,
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config_n_o => config_n_s,
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config_n_o => config_n_s,
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detached_o => detached_s,
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detached_o => detached_s,
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cfg_init_n_i => cfg_init_n_s,
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cfg_init_n_i => cfg_init_n_s,
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cfg_done_i => cfg_done_s,
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cfg_done_i => cfg_done_s,
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dat_done_i => dat_done_s,
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dat_done_i => dat_done_s,
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cfg_clk_o => cfg_clk_s,
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cfg_clk_o => cfg_clk_s,
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cfg_dat_o => cfg_dat_s
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cfg_dat_o => cfg_dat_s
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);
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);
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card_b : card
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card_b : card
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generic map (
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generic map (
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card_type_g => "Full Chip",
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card_type_g => "Full Chip",
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is_sd_card_g => 1
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is_sd_card_g => 1
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)
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)
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port map (
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port map (
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spi_clk_i => spi_clk_s,
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spi_clk_i => spi_clk_s,
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spi_cs_n_i => spi_cs_n_s,
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spi_cs_n_i => spi_cs_n_s,
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spi_data_i => spi_data_to_card_s,
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spi_data_i => spi_data_to_card_s,
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spi_data_o => spi_data_from_card_s
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spi_data_o => spi_data_from_card_s
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);
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);
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rl_b : ram_loader
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rl_b : ram_loader
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port map (
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port map (
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clk_i => rl_clk_s,
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clk_i => rl_clk_s,
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reset_i => reset_s,
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reset_i => reset_s,
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lamp_o => open,
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lamp_o => open,
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cfg_clk_i => cfg_clk_s,
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cfg_clk_i => cfg_clk_s,
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cfg_data_i => cfg_dat_s,
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cfg_data_i => cfg_dat_s,
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start_o => start_s,
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start_o => start_s,
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mode_o => mode_s,
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mode_o => mode_s,
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done_o => dat_done_s,
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done_o => dat_done_s,
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detached_i => detached_s,
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detached_i => detached_s,
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ram_addr_o => open,
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ram_addr_o => open,
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ram_data_b => open,
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ram_data_b => open,
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ram_ce_no => open,
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ram_ce_no => open,
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ram_oe_no => open,
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ram_oe_no => open,
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ram_we_no => open
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ram_we_no => open
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);
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);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Clock Generator
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-- Clock Generator
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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clk: process
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clk: process
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begin
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begin
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clk_s <= '0';
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clk_s <= '0';
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wait for period_c / 2;
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wait for period_c / 2;
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clk_s <= '1';
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clk_s <= '1';
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wait for period_c / 2;
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wait for period_c / 2;
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end process clk;
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end process clk;
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rl_clk: process
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rl_clk: process
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begin
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begin
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rl_clk_s <= '0';
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rl_clk_s <= '0';
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wait for rl_period_c / 2;
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wait for rl_period_c / 2;
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rl_clk_s <= '1';
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rl_clk_s <= '1';
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wait for rl_period_c / 2;
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wait for rl_period_c / 2;
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end process rl_clk;
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end process rl_clk;
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|
|
|
|
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Reset Generator
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-- Reset Generator
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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reset: process
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reset: process
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begin
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begin
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if reset_level_c = 0 then
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if reset_level_c = 0 then
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reset_s <= '0';
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reset_s <= '0';
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else
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else
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reset_s <= '1';
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reset_s <= '1';
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end if;
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end if;
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|
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wait for period_c * 4 + 10 ns;
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wait for period_c * 4 + 10 ns;
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|
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reset_s <= not reset_s;
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reset_s <= not reset_s;
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|
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wait;
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wait;
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end process reset;
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end process reset;
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|
|
|
|
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- End of Simulation
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-- End of Simulation
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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eos: process
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eos: process
|
begin
|
begin
|
wait for 4 ms;
|
wait for 4 ms;
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assert false
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assert false
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report "No checks have been performed. Investigate waveforms."
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report "No checks have been performed. Investigate waveforms."
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severity note;
|
severity note;
|
assert false
|
assert false
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report "End of simulation."
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report "End of simulation."
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severity failure;
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severity failure;
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end process eos;
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end process eos;
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end behav;
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end behav;
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|
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|
|
-------------------------------------------------------------------------------
|
|
-- File History:
|
|
--
|
|
-- $Log: not supported by cvs2svn $
|
|
-------------------------------------------------------------------------------
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|
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No newline at end of file
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No newline at end of file
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