-- synthesis library lib
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-- synthesis library lib
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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-- Project : SPI receivers master
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-- Project : SPI receivers master
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-- Author : AlexRayne
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-- Author : AlexRayne
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-- Date : 2009.03.16.03
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-- Date : 2009.03.16.03
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-- File :
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-- File :
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-- Design :
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-- Design :
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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-- Description : (win1251) SPI ìàñòåð-ïðèåìíèê ñ ìèíèìàëüíûìè çàòðàòàìè ðåñóðñîâ.
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-- Description : (win1251) SPI ìàñòåð-ïðèåìíèê ñ ìèíèìàëüíûìè çàòðàòàìè ðåñóðñîâ.
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-- è âîçìîæíîñòüþ âûäà÷è shut-down ïîñûëêè. Ïðåíàçíà÷åíî äëÿ çàãðóçêè ÀÖÏ AD747x.
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-- è âîçìîæíîñòüþ âûäà÷è shut-down ïîñûëêè. Ïðåíàçíà÷åíî äëÿ çàãðóçêè ÀÖÏ AD747x.
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-- Ìîæåò çàãðóæàòü íàñòðàèâàåìóþ ÷àñòü SPI ïîñëåäîâàòåëüíîñòè (êóñîê).
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-- Ìîæåò çàãðóæàòü íàñòðàèâàåìóþ ÷àñòü SPI ïîñëåäîâàòåëüíîñòè (êóñîê).
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-- ôîðìèðóåò ïîñëåäîâàòåëüíîñòü âõîæäåíèÿ è âûõîäà èç ïîñûëêè ñèãíàëîâ nSS è SCK:
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-- ôîðìèðóåò ïîñëåäîâàòåëüíîñòü âõîæäåíèÿ è âûõîäà èç ïîñûëêè ñèãíàëîâ nSS è SCK:
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-- ïîñëå ïîñûëêà îáîçíà÷àåòñÿ àêòèâíûì nSS('0'), íà ñòàðòå ïîñûëêè SCK='1' ïîëòàêòà
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-- ïîñûëêà îáîçíà÷àåòñÿ àêòèâíûì nSS('0'), íà ñòàðòå ïîñûëêè SCK='1' ïîëòàêòà
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-- çàãðóæàþòñÿ áèòû ïî ïåðåäíåìó ôðîíòó SCK, ïîñëåäíèé áèò ïîñûëêè íåèìååò çàäíåãî
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-- çàãðóæàþòñÿ áèòû ïî ïåðåäíåìó ôðîíòó SCK, ïîñëåäíèé áèò ïîñûëêè íåèìååò çàäíåãî
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-- ôðîíòà, SCK = '1' âñå ïàññèâíîå âðåìÿ.
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-- ôðîíòà, SCK = '1' âñå ïàññèâíîå âðåìÿ.
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-- Description : SPI master-receiver minimalistic costs
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-- Description : SPI master-receiver minimalistic costs
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-- intended for loading ADC AD747x, capable produce shut-down frames.
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-- intended for loading ADC AD747x, capable produce shut-down frames.
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-- can load tunable part of frame. generate entry/exit sequences on nSS, SCK:
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-- can load tunable part of frame. generate entry/exit sequences on nSS, SCK:
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-- activate nSS='0' on frame transfer, SCK='1' for half clock cycle at frame start,
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-- activate nSS='0' on frame transfer, SCK='1' for half clock cycle at frame start,
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-- data loads on rising front SCK, last frame bit have no falling edge SCK,
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-- data loads on rising front SCK, last frame bit have no falling edge SCK,
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-- SCK='1' durung inactive period.
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-- SCK='1' durung inactive period.
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-- SDLen, SDMax:
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-- sets len of short spi sequence for poweroff purposes short (SDLen) and maximum (SDMax) length
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-- QuietLen:
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-- requred TimeOut before start
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-- Start:
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--Start lock on rising CLK, and changes ignores during transmition. if one still high after transmition
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-- ends, then new frame starts after QuietLen timeout if ContinueStart not active
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-- ContinueStart:
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-- if false then spi produce controling sequense of xfer entry and inter-frame pause
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-- else spi start new frame xfer immeidate after completing current frame
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-- ShutDown
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-- locks by high level, after Shuting down complete new SutDown sequence can be forced by Start
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-- if one activate during transmition, then it forces current frame to close if it can (beetween SDLen..SDMax bits)
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-- or generate short shutdown frame after completing current frae else
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-- Ready:
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-- rising edge of ready can be used for loading DQ data to dest.
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-- Shift:
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-- shift clock for internal data register intended to expand load logic to parallel loading registers,
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-- to make a multi chanel reciever
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-- Sleeping
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-- State of ADC power mode - is it shutdowned.
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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-- $Log$
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-- $Log$
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--------------------------------------------------------------------
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--------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_1164.all;
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-- Entity Declaration
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-- Entity Declaration
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ENTITY AdcRecv IS
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ENTITY AdcRecv IS
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-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
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-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
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GENERIC(
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GENERIC(
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SPILen : positive := 16;
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SPILen : positive := 16;
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DataLen : positive := 16;
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DataLen : positive := 16;
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DataOffset : natural := 0;
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DataOffset : natural := 0;
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-- ShutDownLen sets len of short spi sequence for poweroff purposes
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SDLen : natural := 1;
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SDLen : natural := 1;
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SDMax : natural := 10;
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SDMax : natural := 10;
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-- requred TimeOut before start
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QuietLen : natural := 1
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QuietLen : natural := 1
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);
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);
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PORT
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PORT
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(
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(
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CLK : IN STD_LOGIC;
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CLK : IN STD_LOGIC;
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Start : IN STD_LOGIC;
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Start : IN STD_LOGIC;
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-- if false then spi produce controling sequense of xfer entry and inter-frame pause
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-- else spi start new frame xfer immeidate after completing current frame
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ContinueStart : in STD_LOGIC := '0';
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ContinueStart : in STD_LOGIC := '0';
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ShutDown: IN STD_LOGIC;
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ShutDown: IN STD_LOGIC;
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reset : IN STD_LOGIC;
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reset : IN STD_LOGIC;
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SDI : IN STD_LOGIC;
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SDI : IN STD_LOGIC;
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SCK : OUT STD_LOGIC;
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SCK : OUT STD_LOGIC;
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nSS : OUT STD_LOGIC;
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nSS : OUT STD_LOGIC;
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DQ : OUT std_logic_vector(DataLen-1 downto 0);--STD_LOGIC_2D(Chanels-1 downto 0, DataLen-1 downto 0);
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DQ : OUT std_logic_vector(DataLen-1 downto 0);--STD_LOGIC_2D(Chanels-1 downto 0, DataLen-1 downto 0);
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-- rising edge of ready can be used for loading DQ data to dest.
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Ready : OUT STD_LOGIC;
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Ready : OUT STD_LOGIC;
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-- used to expand load logic to parallel loading registers, to make a multi chanel reciever
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Shift : OUT STD_LOGIC;
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Shift : OUT STD_LOGIC
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Sleeping : OUT STD_LOGIC
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);
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);
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-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
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-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
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END AdcRecv;
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END AdcRecv;
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-- Architecture Body
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-- Architecture Body
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ARCHITECTURE BEH OF AdcRecv IS
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ARCHITECTURE BEH OF AdcRecv IS
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signal SS : std_logic;
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signal SS : std_logic;
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signal Data : std_logic_vector(DataLen-1 downto 0);
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signal Data : std_logic_vector(DataLen-1 downto 0);
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signal iSCK : std_logic;
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signal iSCK : std_logic;
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signal iReady : std_logic;
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signal iReady : std_logic;
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subtype BitIndex is natural range 0 to SPILen-1;
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subtype BitIndex is natural range 0 to SPILen-1;
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signal BitNo : BitIndex;
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signal BitNo : BitIndex;
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subtype QuietIndex is natural range 0 to QuietLen;
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subtype QuietIndex is natural range 0 to QuietLen;
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signal QuietCnt : QuietIndex;
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signal QuietCnt : QuietIndex;
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signal QuietOk : std_logic;
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signal QuietOk : std_logic;
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signal isLastBit : std_logic;
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signal isLastBit : std_logic;
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signal isLastDataBit: std_logic;
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signal isLastDataBit: std_logic;
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signal isFirstBit : std_logic;
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signal isFirstBit : std_logic;
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signal Transfer : std_logic := '0';
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signal Transfer : std_logic := '0';
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signal PrepTransfer : std_logic := '0';
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signal PrepTransfer : std_logic := '0';
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signal ReceiveWindow : std_logic := '0';
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signal ReceiveWindow : std_logic := '0';
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type States is ( stSerLoading, stQuietCheck); --stReady,
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type States is ( stSerLoading, stQuietCheck); --stReady,
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signal FSMState : States;
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signal FSMState : States;
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signal NextState : States;
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signal NextState : States;
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signal SDEnough : std_logic;
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signal SDEnough : std_logic;
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signal SDDone : std_logic;
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signal SDDone : std_logic;
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signal NeedSD : std_logic;
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signal NeedSD : std_logic;
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signal Enable : std_logic;
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signal Enable : std_logic;
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begin
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begin
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BitCounter : process(CLK, reset, Enable, Transfer, isLastBit, FSMState) is begin
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BitCounter : process(CLK, reset, Enable, Transfer, isLastBit, FSMState) is begin
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if (reset = '1') or (FSMState = stQuietCheck) then -- (Enable = '0') then
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if (reset = '1') or (FSMState = stQuietCheck) then -- (Enable = '0') then
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BitNo <= 0;
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BitNo <= 0;
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else
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else
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if falling_edge(CLK) then
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if falling_edge(CLK) then
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if isLastBit = '1' then
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if isLastBit = '1' then
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BitNo <= 0;
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BitNo <= 0;
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else
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else
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if Transfer = '1' then
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if Transfer = '1' then
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BitNo <= BitNo+1;
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BitNo <= BitNo+1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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isFirstBit <= '1' when (BitNo = 0) else '0';
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isFirstBit <= '1' when (BitNo = 0) else '0';
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isLastBit <= '1' when (BitNo = SPILen-1) else '0';
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isLastBit <= '1' when (BitNo = SPILen-1) else '0';
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isLastDataBit <= '1'when (BitNo = DataOffset + DataLen-1) else '0';
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isLastDataBit <= '1'when (BitNo = DataOffset + DataLen-1) else '0';
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ReceiveWindow <= '1' when (BitNo >= DataOffset) and (BitNo <= DataOffset + DataLen-1)
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ReceiveWindow <= '1' when (BitNo >= DataOffset) and (BitNo <= DataOffset + DataLen-1)
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else '0';
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else '0';
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SDEnough <= '1' when (BitNo >= SDLen) and (BitNo < SDMax) else '0';
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SDEnough <= '1' when (BitNo >= SDLen) and (BitNo < SDMax) else '0';
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SDmonitor : process(SS, enable, iSCK, NeedSD, SDEnough, Reset) is begin
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SDmonitor : process(SS, enable, iSCK, NeedSD, SDEnough, Reset) is begin
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if (reset = '1') or (iSCK = '0') then
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if (reset = '1') or (iSCK = '0') then
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SDDone <= '0';
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SDDone <= '0';
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elsif falling_edge(enable) then
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elsif falling_edge(enable) then
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SDDone <= SDEnough;
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SDDone <= SDEnough;
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end if;
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end if;
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end process;
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end process;
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Sleeping <= SDDone;
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Qsafer: if QuietLen > 1 generate
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Qsafer: if QuietLen > 1 generate
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QuietOk <= '1' when (QuietCnt >= QuietLen) else '0';
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QuietOk <= '1' when (QuietCnt >= QuietLen) else '0';
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QuietCounter: process(FSMState, reset, CLK, QuietOk) is begin
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QuietCounter: process(FSMState, reset, CLK, QuietOk) is begin
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if (reset = '1')
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if (reset = '1')
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or (FSMState = stSerLoading)
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or (FSMState = stSerLoading)
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then
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then
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QuietCnt <= 0;
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QuietCnt <= 0;
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else
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else
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if rising_edge(CLK) then
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if rising_edge(CLK) then
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if QuietOk = '0' then
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if QuietOk = '0' then
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QuietCnt <= QuietCnt+1;
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QuietCnt <= QuietCnt+1;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end generate;
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end generate;
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EmptyQsafer: if QuietLen <= 1 generate
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EmptyQsafer: if QuietLen <= 1 generate
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QuietOk <= '1';
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QuietOk <= '1';
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end generate;
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end generate;
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EnableReg: process(Start, NeedSD, iReady, NextState, FSMState, CLK, Reset) is begin
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EnableReg: process(Start, NeedSD, iReady, NextState, FSMState, CLK, Reset) is begin
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if (reset = '1') then
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if (reset = '1') then
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Enable <= '0';
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Enable <= '0';
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elsif rising_edge(CLK) then
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elsif rising_edge(CLK) then
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if (iReady and (Start or NeedSD)) = '1' then
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if (iReady and (Start or NeedSD)) = '1' then
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Enable <= '1';
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Enable <= '1';
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else
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else
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if (FSMState = stSerLoading) and (NextState /= stSerLoading) then
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if (FSMState = stSerLoading) and (NextState /= stSerLoading) then
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Enable <= '0';
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Enable <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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SDRequest: process(ShutDown, SDDone, Reset) is begin
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SDRequest: process(ShutDown, SDDone, Reset) is begin
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if (Reset = '1') or (SDDone = '1') then
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if (Reset = '1') or (SDDone = '1') then
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NeedSD <= '0';
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NeedSD <= '0';
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elsif (ShutDown = '1') and (SDDone = '0') then
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elsif (ShutDown = '1') and (SDDone = '0') then
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NeedSD <= '1';
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NeedSD <= '1';
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end if;
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end if;
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end process;
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end process;
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-- NeedSD <= ShutDown and not SDDone;
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-- NeedSD <= ShutDown and not SDDone;
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-- NeedSD <= '1' when ShutDown and not SDDone else
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-- NeedSD <= '1' when ShutDown and not SDDone else
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-- '0' when ;
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-- '0' when ;
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FSMStepper : process(NextState, CLK, Reset) is begin
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FSMStepper : process(NextState, CLK, Reset) is begin
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if reset = '1' then
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if reset = '1' then
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FSMState <= stQuietCheck;
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FSMState <= stQuietCheck;
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elsif falling_edge(CLK) then
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elsif falling_edge(CLK) then
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FSMState <= NextState;
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FSMState <= NextState;
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end if;
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end if;
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end process;
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end process;
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FSM : process(FSMState, CLK, QuietOk, isLastBit, ContinueStart
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FSM : process(FSMState, CLK, QuietOk, isLastBit, ContinueStart
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, ShutDown, SDEnough, Start, NeedSD, Reset, Enable)
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, ShutDown, SDEnough, Start, NeedSD, Reset, Enable)
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is begin
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is begin
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case FSMState is
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case FSMState is
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when stSerLoading =>
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when stSerLoading =>
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if (ShutDown = '1') and (SDEnough = '1') then
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if (ShutDown = '1') and (SDEnough = '1') then
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NextState <= stQuietCheck;
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NextState <= stQuietCheck;
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elsif (isLastBit = '1') then
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elsif (isLastBit = '1') then
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if ContinueStart = '0' then
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if ContinueStart = '0' then
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NextState <= stQuietCheck;
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NextState <= stQuietCheck;
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else
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else
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NextState <= stSerLoading;--stReady;
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NextState <= stSerLoading;--stReady;
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end if;
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end if;
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else
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else
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NextState <= stSerLoading;
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NextState <= stSerLoading;
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end if;
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end if;
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when stQuietCheck =>
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when stQuietCheck =>
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if (QuietOk = '1') then
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if (QuietOk = '1') then
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if ((Enable = '1') or (NeedSD = '1')) then
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if ((Enable = '1') or (NeedSD = '1')) then
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NextState <= stSerLoading;
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NextState <= stSerLoading;
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else
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else
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NextState <= stQuietCheck;--stReady;
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NextState <= stQuietCheck;--stReady;
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end if;
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end if;
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else
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else
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NextState <= stQuietCheck;
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NextState <= stQuietCheck;
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end if;
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end if;
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when others =>
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when others =>
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NextState <= stQuietCheck;
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NextState <= stQuietCheck;
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end case;
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end case;
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end process;
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end process;
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Transfer <= '1' when (FSMState = stSerLoading) else '0';
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Transfer <= '1' when (FSMState = stSerLoading) else '0';
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-- SS must contain gap with '1' about 1/2cycle on SCK at start and end of frames
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-- SS must contain gap with '1' about 1/2cycle on SCK at start and end of frames
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SS <= Transfer or Enable;
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SS <= Transfer or Enable;
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iSCK <= CLK or not Enable; --when (FSMState = stSerLoading) else '1';
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iSCK <= CLK or not Enable; --when (FSMState = stSerLoading) else '1';
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nSS <= not SS;
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nSS <= not SS;
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SCK <= iSCK;
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SCK <= iSCK;
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DataCell : process (Data, CLK, reset, ReceiveWindow, SS) is begin
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DataCell : process (Data, CLK, reset, ReceiveWindow, SS) is begin
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if reset = '1' then
|
if reset = '1' then
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Data <= (others => '0');
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Data <= (others => '0');
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elsif rising_edge(CLK) then
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elsif rising_edge(CLK) then
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if (ReceiveWindow = '1') and (SS = '1') then
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if (ReceiveWindow = '1') and (SS = '1') then
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Data(Data'high downto 1) <= Data(Data'high-1 downto 0);
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Data(Data'high downto 1) <= Data(Data'high-1 downto 0);
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Data(0) <= SDI;
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Data(0) <= SDI;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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DQ <= Data;
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DQ <= Data;
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Shift <= CLK and ReceiveWindow;
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Shift <= CLK and ReceiveWindow;
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readyMoitor: process(CLK, FSMState, isFirstbit, isLastDataBit, Reset) is begin
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readyMoitor: process(CLK, FSMState, isFirstbit, isLastDataBit, Reset) is begin
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if (reset = '1') or (FSMState = stQuietCheck) then
|
if (reset = '1') or (FSMState = stQuietCheck) then
|
iready <= '1';
|
iready <= '1';
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elsif (FSMState = stSerLoading) and (isFirstbit = '1') and (CLK = '1') then
|
elsif (FSMState = stSerLoading) and (isFirstbit = '1') and (CLK = '1') then
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iready <= '0';
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iready <= '0';
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elsif falling_edge(CLK) then
|
elsif falling_edge(CLK) then
|
if isLastDataBit = '1' then
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if isLastDataBit = '1' then
|
iready <= '1';
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iready <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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Ready <= iReady;
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Ready <= iReady;
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end architecture BEH;
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end architecture BEH;
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