//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// SPI GPIO IP Core ////
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//// SPI GPIO IP Core ////
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//// ////
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//// ////
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//// This file is part of the spigpio project ////
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//// This file is part of the spigpio project ////
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//// http://www.opencores.org/project,spislave ////
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//// http://www.opencores.org/project,spislave ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Implementation of spislave IP core according to ////
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//// Implementation of spislave IP core according to ////
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//// spigpio IP core specification document. ////
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//// spigpio IP core specification document. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - ////
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//// - ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Sivakumar.B , email: siva@zilogic.com ////
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//// - Sivakumar.B , email: siva@zilogic.com ////
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//// email: siva12@opencores.org ////
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//// email: siva12@opencores.org ////
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//// Engineer Zilogic systems,chennai. www.zilogic.com ////
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//// Engineer Zilogic systems,chennai. www.zilogic.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2009 Zilogic Systems and OPENCORES.ORG ////
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//// Copyright (C) 2009 Zilogic Systems and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// RTL program for SPI SLAVE -- shift 8 bit register ////
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//// RTL program for SPI GPIO -- ////
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`define P0_OP 7'b0000000 //0x00
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`define P0_OP 7'b0000000 //0x00
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`define P1_OP 7'b0000001 //0x01
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`define P1_OP 7'b0000001 //0x01
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`define P2_OP 7'b0000010 //0x02
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`define P2_OP 7'b0000010 //0x02
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`define P3_OP 7'b0000011 //0x03
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`define P3_OP 7'b0000011 //0x03
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`define P4_OP 7'b0000100 //0x04
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`define P4_OP 7'b0000100 //0x04
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`define P5_OP 7'b0000101 //0x05
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`define P5_OP 7'b0000101 //0x05
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`define P6_OP 7'b0000110 //0x06
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`define P6_OP 7'b0000110 //0x06
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`define P7_OP 7'b0000111 //0x07
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`define P7_OP 7'b0000111 //0x07
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`define P8_OP 7'b0001000 //0x08
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`define P8_OP 7'b0001000 //0x08
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`define P9_OP 7'b0001001 //0x09
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`define P9_OP 7'b0001001 //0x09
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`define P0_P9_OP 7'b0001010 //0x0A
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`define P0_P9_OP 7'b0001010 //0x0A
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`define P0_P3_OP 7'b0001011 //0x0B
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`define P0_P3_OP 7'b0001011 //0x0B
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`define P4_P7_OP 7'b0001100 //0x0C
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`define P4_P7_OP 7'b0001100 //0x0C
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`define P8_P9_OP 7'b0001101 //0x0D
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`define P8_P9_OP 7'b0001101 //0x0D
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`define PO_P7_IP 7'b0001110 //0x0E
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`define PO_P7_IP 7'b0001110 //0x0E
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`define P8_P9_IP 7'b0001111 //0x0F
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`define P8_P9_IP 7'b0001111 //0x0F
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`define RAM 7'b0010011 //0x13
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`define RAM 7'b0010011 //0x13
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module spigpio(clk, cs, sr_in, gpioin, gpioout, sr_out);
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module spigpio(clk, cs, sr_in, gpioin, gpioout, sr_out);
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input clk, cs;
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input clk, cs;
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input sr_in;
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input sr_in;
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input [9:0] gpioin;
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input [9:0] gpioin;
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output sr_out;
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output sr_out;
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output [9:0] gpioout;
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output [9:0] gpioout;
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reg [9:0] gpioout;
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reg [9:0] gpioout;
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reg sr_out;
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reg sr_out;
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reg [7:0] ram;
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reg [7:0] ram;
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wire [6:0] addr;
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wire [6:0] addr;
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wire [7:0] data;
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wire [7:0] data;
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wire rw;
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wire rw;
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reg [15:0] sr;
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reg [15:0] sr;
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assign rw = sr[15];
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assign rw = sr[15];
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assign addr = sr[14:8];
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assign addr = sr[14:8];
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assign data = sr[7:0];
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assign data = sr[7:0];
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always@(posedge clk or posedge cs)
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always@(posedge clk or posedge cs)
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begin
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begin
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if (cs == 1'b0)
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if (cs == 1'b0)
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begin
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begin
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sr_out <= sr[15];
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sr_out <= sr[15];
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sr[15:1] <= sr[14:0];
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sr[15:1] <= sr[14:0];
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sr[0] <= sr_in;
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sr[0] <= sr_in;
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end
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end
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if (cs == 1'b1)
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if (cs == 1'b1)
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begin
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begin
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if (rw == 1'b0)
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if (rw == 1'b0)
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begin
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begin
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case (addr)
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case (addr)
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`P0_OP : gpioout[0] <= data[0];
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`P0_OP : gpioout[0] <= data[0];
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`P1_OP : gpioout[1] <= data[0];
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`P1_OP : gpioout[1] <= data[0];
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`P2_OP : gpioout[2] <= data[0];
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`P2_OP : gpioout[2] <= data[0];
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`P3_OP : gpioout[3] <= data[0];
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`P3_OP : gpioout[3] <= data[0];
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`P4_OP : gpioout[4] <= data[0];
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`P4_OP : gpioout[4] <= data[0];
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`P5_OP : gpioout[5] <= data[0];
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`P5_OP : gpioout[5] <= data[0];
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`P6_OP : gpioout[6] <= data[0];
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`P6_OP : gpioout[6] <= data[0];
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`P7_OP : gpioout[7] <= data[0];
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`P7_OP : gpioout[7] <= data[0];
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`P8_OP : gpioout[8] <= data[0];
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`P8_OP : gpioout[8] <= data[0];
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`P9_OP : gpioout[9] <= data[0];
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`P9_OP : gpioout[9] <= data[0];
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`P0_P9_OP : gpioout[9:0] <= {data[0], data[0], data[0], data[0], data[0],
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`P0_P9_OP : gpioout[9:0] <= {data[0], data[0], data[0], data[0], data[0],
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data[0], data[0], data[0], data[0], data[0]};
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data[0], data[0], data[0], data[0], data[0]};
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`P0_P3_OP : gpioout[3:0] <= {data[0], data[0], data[0], data[0]};
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`P0_P3_OP : gpioout[3:0] <= {data[0], data[0], data[0], data[0]};
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`P4_P7_OP : gpioout[7:4] <= {data[0], data[0], data[0], data[0]};
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`P4_P7_OP : gpioout[7:4] <= {data[0], data[0], data[0], data[0]};
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`P8_P9_OP : gpioout[9:8] <= {data[0], data[0]};
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`P8_P9_OP : gpioout[9:8] <= {data[0], data[0]};
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`RAM : ram[7:0] <= data[7:0];
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`RAM : ram[7:0] <= data[7:0];
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endcase
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endcase
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end
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end
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if (rw == 1'b1) // READ THE PORT LEVEL
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if (rw == 1'b1) // READ THE PORT LEVEL
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begin
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begin
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case (addr)
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case (addr)
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`P0_OP : sr[7:0] <= {7'b0, gpioout[0]};
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`P0_OP : sr[7:0] <= {7'b0, gpioout[0]};
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`P1_OP : sr[7:0] <= {7'b0, gpioout[1]};
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`P1_OP : sr[7:0] <= {7'b0, gpioout[1]};
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`P2_OP : sr[7:0] <= {7'b0, gpioout[2]};
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`P2_OP : sr[7:0] <= {7'b0, gpioout[2]};
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`P3_OP : sr[7:0] <= {7'b0, gpioout[3]};
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`P3_OP : sr[7:0] <= {7'b0, gpioout[3]};
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`P4_OP : sr[7:0] <= {7'b0, gpioout[4]};
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`P4_OP : sr[7:0] <= {7'b0, gpioout[4]};
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`P5_OP : sr[7:0] <= {7'b0, gpioout[5]};
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`P5_OP : sr[7:0] <= {7'b0, gpioout[5]};
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`P6_OP : sr[7:0] <= {7'b0, gpioout[6]};
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`P6_OP : sr[7:0] <= {7'b0, gpioout[6]};
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`P7_OP : sr[7:0] <= {7'b0, gpioout[7]};
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`P7_OP : sr[7:0] <= {7'b0, gpioout[7]};
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`P8_OP : sr[7:0] <= {7'b0, gpioout[8]};
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`P8_OP : sr[7:0] <= {7'b0, gpioout[8]};
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`P9_OP : sr[7:0] <= {7'b0, gpioout[9]};
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`P9_OP : sr[7:0] <= {7'b0, gpioout[9]};
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`P0_P9_OP : sr[7:0] <= {7'b0, gpioout[0]};
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`P0_P9_OP : sr[7:0] <= {7'b0, gpioout[0]};
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`P0_P3_OP : sr[7:0] <= {7'b0, gpioout[0]};
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`P0_P3_OP : sr[7:0] <= {7'b0, gpioout[0]};
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`P4_P7_OP : sr[7:0] <= {7'b0, gpioout[4]};
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`P4_P7_OP : sr[7:0] <= {7'b0, gpioout[4]};
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`P8_P9_OP : sr[7:0] <= {7'b0, gpioout[8]};
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`P8_P9_OP : sr[7:0] <= {7'b0, gpioout[8]};
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`PO_P7_IP : sr[7:0] <= gpioin[7:0];
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`PO_P7_IP : sr[7:0] <= gpioin[7:0];
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`P8_P9_IP : sr[7:0] <= gpioin[9:8];
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`P8_P9_IP : sr[7:0] <= gpioin[9:8];
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`RAM : sr[7:0] <= ram[7:0];
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`RAM : sr[7:0] <= ram[7:0];
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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