// ------------------------ spiMaster_defines.v ----------------------
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// ------------------------ spiMaster_defines.v ----------------------
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// Version 0.0 - April 2008. Created
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// Version 0.0 - April 2008. Created
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// Version 1.0 - 3rd June 2008. Fixed synchronisation issue between busClk and
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// Version 1.0 - 3rd June 2008. Fixed synchronisation issue between busClk and
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// spiSysClk. Fixed bug in bus accessible reset. Changed names of
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// spiSysClk. Fixed bug in bus accessible reset. Changed names of
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// fifo related modules to avoid conflict with other IP cores.
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// fifo related modules to avoid conflict with other IP cores.
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// Version 1.1 - 23rd August 2008. Modified reset synchronisation. Fixed bug
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// Version 1.1 - 23rd August 2008. Modified reset synchronisation. Fixed bug
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// in wb_ack. Fixed file headers, and added description
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// in wb_ack. Fixed file headers, and added description
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// Version 1.2 - 25th October 2008. Modified readWriteSPIWireData to clock data
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// from the SPI bus on the rising edge of SCLK. This increases the
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// tsetup timing margin when reading SPI data. It turns out that the timing
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// was marginal for some SD cards when using a 24Mhz SPI clock.
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// Problem was exacerbated by the fact that the design prevents the
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// final SPI interface Flipflops being pushed into the IO blocks.
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`define SPI_MASTER_VERSION_NUM 8'h11
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`define SPI_MASTER_VERSION_NUM 8'h12
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`define SPI_SYS_CLK_48MHZ
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`define SPI_SYS_CLK_48MHZ
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//`define SPI_SYS_CLK_30MHZ
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//`define SPI_SYS_CLK_30MHZ
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//memoryMap
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//memoryMap
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`define CTRL_STS_REG_BASE 8'h00
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`define CTRL_STS_REG_BASE 8'h00
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`define RX_FIFO_BASE 8'h10
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`define RX_FIFO_BASE 8'h10
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`define TX_FIFO_BASE 8'h20
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`define TX_FIFO_BASE 8'h20
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`define ADDRESS_DECODE_MASK 8'hf0
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`define ADDRESS_DECODE_MASK 8'hf0
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`define SPI_MASTER_VERSION_REG 8'h00
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`define SPI_MASTER_VERSION_REG 8'h00
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`define SPI_MASTER_CONTROL_REG 8'h01
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`define SPI_MASTER_CONTROL_REG 8'h01
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`define TRANS_TYPE_REG 8'h02
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`define TRANS_TYPE_REG 8'h02
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`define TRANS_CTRL_REG 8'h03
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`define TRANS_CTRL_REG 8'h03
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`define TRANS_STS_REG 8'h04
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`define TRANS_STS_REG 8'h04
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`define TRANS_ERROR_REG 8'h05
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`define TRANS_ERROR_REG 8'h05
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`define DIRECT_ACCESS_DATA_REG 8'h06
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`define DIRECT_ACCESS_DATA_REG 8'h06
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`define SD_ADDR_7_0_REG 8'h07
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`define SD_ADDR_7_0_REG 8'h07
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`define SD_ADDR_15_8_REG 8'h08
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`define SD_ADDR_15_8_REG 8'h08
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`define SD_ADDR_23_16_REG 8'h09
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`define SD_ADDR_23_16_REG 8'h09
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`define SD_ADDR_31_24_REG 8'h0a
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`define SD_ADDR_31_24_REG 8'h0a
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`define SPI_CLK_DEL_REG 8'h0b
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`define SPI_CLK_DEL_REG 8'h0b
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//FifoAddresses
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//FifoAddresses
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`define FIFO_DATA_REG 3'b000
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`define FIFO_DATA_REG 3'b000
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`define FIFO_STATUS_REG 3'b001
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`define FIFO_STATUS_REG 3'b001
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`define FIFO_DATA_COUNT_MSB 3'b010
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`define FIFO_DATA_COUNT_MSB 3'b010
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`define FIFO_DATA_COUNT_LSB 3'b011
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`define FIFO_DATA_COUNT_LSB 3'b011
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`define FIFO_CONTROL_REG 3'b100
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`define FIFO_CONTROL_REG 3'b100
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`ifdef SIM_COMPILE
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`ifdef SIM_COMPILE
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`define SLOW_SPI_CLK 8'h2
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`define SLOW_SPI_CLK 8'h2
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`define FAST_SPI_CLK 8'h00
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`define FAST_SPI_CLK 8'h00
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`define TWO_MS 10'h001
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`define TWO_MS 10'h001
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`define TWO_FIFTY_MS 12'h001
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`define TWO_FIFTY_MS 12'h001
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`define ONE_HUNDRED_MS 12'h00c
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`define ONE_HUNDRED_MS 12'h00c
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`else //not SIM_COMPILE
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`else //not SIM_COMPILE
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`ifdef SPI_SYS_CLK_48MHZ
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`ifdef SPI_SYS_CLK_48MHZ
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// --------------- spiSysClk = 48MHz
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// --------------- spiSysClk = 48MHz
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// if you change the clock frequency you will need to change these constants
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// if you change the clock frequency you will need to change these constants
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// SLOW_SPI_CLK controls the SPI clock at start up.
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// SLOW_SPI_CLK controls the SPI clock at start up.
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// should be aiming for 400KHz
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// should be aiming for 400KHz
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// SLOW_SPI_CLK = (spiSysClk / (400KHz * 2)) - 1
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// SLOW_SPI_CLK = (spiSysClk / (400KHz * 2)) - 1
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`define SLOW_SPI_CLK 8'h3b
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`define SLOW_SPI_CLK 8'h3b
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// controls the SPI clock after init is complete.
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// controls the SPI clock after init is complete.
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// should be aiming for 24MHz ?
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// should be aiming for 24MHz ?
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// controls the SPI clock after init is complete.
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// controls the SPI clock after init is complete.
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// should be aiming for 24MHz ?
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// should be aiming for 24MHz ?
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// if spiSysClk >= 48MHz
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// if spiSysClk >= 48MHz
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// FAST_SPI_CLK = (spiSysClk / (24MHz * 2)) - 1
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// FAST_SPI_CLK = (spiSysClk / (24MHz * 2)) - 1
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// else FAST_SPI_CLK = 0
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// else FAST_SPI_CLK = 0
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`define FAST_SPI_CLK 8'h00
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`define FAST_SPI_CLK 8'h00
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// TWO_MS = ((2mS * spiSysClk) / 256) - 1
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// TWO_MS = ((2mS * spiSysClk) / 256) - 1
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`define TWO_MS 10'h177
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`define TWO_MS 10'h177
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// TWO_FIFTY_MS = ((250mS * spiSysClk) / 65536) - 1
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// TWO_FIFTY_MS = ((250mS * spiSysClk) / 65536) - 1
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`define TWO_FIFTY_MS 12'h0b6
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`define TWO_FIFTY_MS 12'h0b6
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// ONE_HUNDRED_MS = ((100mS * spiSysClk) / 65536) - 1
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// ONE_HUNDRED_MS = ((100mS * spiSysClk) / 65536) - 1
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`define ONE_HUNDRED_MS 12'h048
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`define ONE_HUNDRED_MS 12'h048
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`else //not SPI_SYS_CLK_48MHZ
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`else //not SPI_SYS_CLK_48MHZ
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`ifdef SPI_SYS_CLK_30MHZ
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`ifdef SPI_SYS_CLK_30MHZ
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// --------------- spiSysClk = 30MHz
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// --------------- spiSysClk = 30MHz
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`define SLOW_SPI_CLK 8'h24
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`define SLOW_SPI_CLK 8'h24
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`define FAST_SPI_CLK 8'h00
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`define FAST_SPI_CLK 8'h00
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`define TWO_MS 10'h0e9
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`define TWO_MS 10'h0e9
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`define TWO_FIFTY_MS 12'h071
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`define TWO_FIFTY_MS 12'h071
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`define ONE_HUNDRED_MS 12'h02c
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`define ONE_HUNDRED_MS 12'h02c
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`endif //SPI_SYS_CLK_30MHZ
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`endif //SPI_SYS_CLK_30MHZ
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`endif //SPI_SYS_CLK_48MHZ
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`endif //SPI_SYS_CLK_48MHZ
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`endif //SIM_COMPILE
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`endif //SIM_COMPILE
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`ifdef SIM_COMPILE
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`ifdef SIM_COMPILE
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`define SD_INIT_START_SEQ_LEN 8'h03
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`define SD_INIT_START_SEQ_LEN 8'h03
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`define MAX_8_BIT 8'h08
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`define MAX_8_BIT 8'h08
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`else
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`else
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`define SD_INIT_START_SEQ_LEN 8'ha0
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`define SD_INIT_START_SEQ_LEN 8'ha0
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`define MAX_8_BIT 8'hff
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`define MAX_8_BIT 8'hff
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`endif
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`endif
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`define WR_RESP_TOUT 12'hf00
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`define WR_RESP_TOUT 12'hf00
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`define NO_BLOCK_REQ 2'b00
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`define NO_BLOCK_REQ 2'b00
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`define WRITE_SD_BLOCK 2'b01
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`define WRITE_SD_BLOCK 2'b01
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`define READ_SD_BLOCK 2'b10
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`define READ_SD_BLOCK 2'b10
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`define READ_NO_ERROR 2'b00
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`define READ_NO_ERROR 2'b00
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`define READ_CMD_ERROR 2'b01
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`define READ_CMD_ERROR 2'b01
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`define READ_TOKEN_ERROR 2'b10
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`define READ_TOKEN_ERROR 2'b10
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`define WRITE_NO_ERROR 2'b00
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`define WRITE_NO_ERROR 2'b00
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`define WRITE_CMD_ERROR 2'b01
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`define WRITE_CMD_ERROR 2'b01
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`define WRITE_DATA_ERROR 2'b10
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`define WRITE_DATA_ERROR 2'b10
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`define WRITE_BUSY_ERROR 2'b11
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`define WRITE_BUSY_ERROR 2'b11
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`define TRANS_NOT_BUSY 1'b0
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`define TRANS_NOT_BUSY 1'b0
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`define TRANS_BUSY 1'b1
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`define TRANS_BUSY 1'b1
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`define TRANS_START 1'b1
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`define TRANS_START 1'b1
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`define TRANS_STOP 1'b0
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`define TRANS_STOP 1'b0
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`define DIRECT_ACCESS 2'b00
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`define DIRECT_ACCESS 2'b00
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`define INIT_SD 2'b01
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`define INIT_SD 2'b01
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`define RW_READ_SD_BLOCK 2'b10
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`define RW_READ_SD_BLOCK 2'b10
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`define RW_WRITE_SD_BLOCK 2'b11
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`define RW_WRITE_SD_BLOCK 2'b11
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`define INIT_NO_ERROR 2'b00
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`define INIT_NO_ERROR 2'b00
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`define INIT_CMD0_ERROR 2'b01
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`define INIT_CMD0_ERROR 2'b01
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`define INIT_CMD1_ERROR 2'b10
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`define INIT_CMD1_ERROR 2'b10
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`define TX_FIFO_DEPTH 512
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`define TX_FIFO_DEPTH 512
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`define TX_FIFO_ADDR_WIDTH 9
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`define TX_FIFO_ADDR_WIDTH 9
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`define RX_FIFO_DEPTH 512
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`define RX_FIFO_DEPTH 512
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`define RX_FIFO_ADDR_WIDTH 9
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`define RX_FIFO_ADDR_WIDTH 9
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