/*
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/*
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1942 simple board setup in order to test SQMUSIC.
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1942 simple board setup in order to test SQMUSIC.
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Requirements:
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Requirements:
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TV80, Z80 Verilog module
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TV80, Z80 Verilog module
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Dump of Z80 ROM from 1942 board
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Dump of Z80 ROM from 1942 board
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(c) Jose Tejada Gomez, 9th May 2013
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(c) Jose Tejada Gomez, 9th May 2013
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You can use this file following the GNU GENERAL PUBLIC LICENSE version 3
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You can use this file following the GNU GENERAL PUBLIC LICENSE version 3
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Read the details of the license in:
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Read the details of the license in:
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http://www.gnu.org/licenses/gpl.txt
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http://www.gnu.org/licenses/gpl.txt
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Send comments to: jose.tejada@ieee.org
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Send comments to: jose.tejada@ieee.org
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*/
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*/
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module sound1942;
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module sound1942;
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// inputs to Z80
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// inputs to Z80
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reg reset_n, clk, int_n, sound_clk;
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reg reset_n, clk, int_n, sound_clk;
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parameter dump_text = 1; // set to 1 to dump data to use log2wav later
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initial begin
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initial begin
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/* $dumpfile("dump.lxt");
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/* $dumpfile("dump.lxt");
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$dumpvars(1,pwm0);
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$dumpvars(1,pwm0);
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$dumpvars(1,pwm1);*/
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$dumpvars(1,pwm1);*/
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// $dumpvars();
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// $dumpvars();
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// $dumpon;
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// $dumpon;
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// $shm_open("1942.shm");
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// $shm_open("1942.shm");
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// $shm_probe( sound1942, "ACTFS" );
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// $shm_probe( sound1942, "ACTFS" );
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reset_n=0;
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reset_n=0;
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#1500 reset_n=1;
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#1500 reset_n=1;
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$display("1942 START");
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// change finish time depending on song
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// change finish time depending on song
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//#4e6 $finish;
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//#0.1e9 $finish;
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#6e9 $finish;
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#7e9 $finish;
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end
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end
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always begin // main clock
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always begin // main clock
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clk=0;
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clk=0;
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forever clk = #167 ~clk;
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forever clk = #167 ~clk;
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end
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end
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always begin // sound clock
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always begin // sound clock
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sound_clk=0;
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sound_clk=0;
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forever sound_clk = #334 ~sound_clk;
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forever sound_clk = #334 ~sound_clk;
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end
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end
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parameter int_low_time=167*2*80;
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parameter int_low_time=167*2*80;
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always begin // interrupt clock
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always begin // interrupt clock
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int_n=1;
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int_n=1;
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forever begin
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forever begin
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#(4166667-int_low_time) int_n=0; // 240Hz
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#(4166667-int_low_time) int_n=0; // 240Hz
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//$display("IRQ request @ %t us",$time/1e6);
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//$display("IRQ request @ %t us",$time/1e6);
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#(int_low_time) int_n=1;
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#(int_low_time) int_n=1;
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end
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end
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end
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end
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wire [3:0] ay0_a, ay0_b, ay0_c, ay1_a, ay1_b, ay1_c;
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wire [3:0] ay0_a, ay0_b, ay0_c, ay1_a, ay1_b, ay1_c;
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computer_1942 #(0) game( .clk(clk), .sound_clk(sound_clk),
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computer_1942 #(0) game( .clk(clk), .sound_clk(sound_clk),
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.int_n(int_n), .reset_n(reset_n),
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.int_n(int_n), .reset_n(reset_n),
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.ay0_a(ay0_a), .ay0_b(ay0_b), .ay0_c(ay0_c),
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.ay0_a(ay0_a), .ay0_b(ay0_b), .ay0_c(ay0_c),
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.ay1_a(ay1_a), .ay1_b(ay1_b), .ay1_c(ay1_c) );
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.ay1_a(ay1_a), .ay1_b(ay1_b), .ay1_c(ay1_c) );
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// sound amplifier:
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// sound amplifier:
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/*
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/*
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wire [15:0] amp0_y, amp1_y;
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wire [15:0] amp0_y, amp1_y;
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SQM_AMP amp0( .A(ay0_a), .B(ay0_b), .C(ay0_c), .Y( amp0_y ));
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SQM_AMP amp0( .A(ay0_a), .B(ay0_b), .C(ay0_c), .Y( amp0_y ));
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SQM_AMP amp1( .A(ay1_a), .B(ay1_b), .C(ay1_c), .Y( amp1_y ));
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SQM_AMP amp1( .A(ay1_a), .B(ay1_b), .C(ay1_c), .Y( amp1_y ));
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always #22676 $display("%d", amp0_y+amp1_y ); // 44.1kHz sample
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always #22676 $display("%d", amp0_y+amp1_y ); // 44.1kHz sample
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*/
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*/
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reg vhf_clk;
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reg vhf_clk;
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always begin
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always begin
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vhf_clk=0;
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vhf_clk=0;
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forever begin
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forever begin
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if( vhf_clk ) begin
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if( vhf_clk && dump_text ) begin
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$display("%d, %d, %d, %d, %d, %d",
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$display("%d, %d, %d, %d, %d, %d",
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pwm0_a, pwm0_b, pwm0_c, pwm1_a, pwm1_b, pwm1_c );
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pwm0_a, pwm0_b, pwm0_c, pwm1_a, pwm1_b, pwm1_c );
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end
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end
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#10 vhf_clk <= ~vhf_clk; // 50MHz
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#10 vhf_clk <= ~vhf_clk; // 50MHz
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end
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end
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end
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end
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SQM_PWM_1 a0pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay0_a), .pwm(pwm0_a) );
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SQM_PWM_1 a0pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay0_a), .pwm(pwm0_a) );
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SQM_PWM_1 b0pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay0_b), .pwm(pwm0_b) );
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SQM_PWM_1 b0pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay0_b), .pwm(pwm0_b) );
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SQM_PWM_1 c0pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay0_c), .pwm(pwm0_c) );
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SQM_PWM_1 c0pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay0_c), .pwm(pwm0_c) );
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SQM_PWM_1 a1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_a), .pwm(pwm1_a) );
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SQM_PWM_1 a1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_a), .pwm(pwm1_a) );
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SQM_PWM_1 b1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_b), .pwm(pwm1_b) );
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SQM_PWM_1 b1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_b), .pwm(pwm1_b) );
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SQM_PWM_1 c1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_c), .pwm(pwm1_c) );
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SQM_PWM_1 c1pwm( .clk(vhf_clk), .reset_n(reset_n), .din(ay1_c), .pwm(pwm1_c) );
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endmodule
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endmodule
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/////////////////////////////////////////////////////
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module computer_1942
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#(parameter dump_regs=0) // set to 1 to dump sqmusic registers
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(
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input clk,
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input sound_clk,
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input reset_n,
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input int_n,
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output [3:0] ay0_a,
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output [3:0] ay0_b,
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output [3:0] ay0_c,
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output [3:0] ay1_a,
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output [3:0] ay1_b,
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output [3:0] ay1_c
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);
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reg wait_n, nmi_n, busrq_n;
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wire [7:0]cpu_in, cpu_out;
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wire [15:0]adr;
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wire m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n;
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wire bus_error;
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wire [3:0] ay0_a, ay0_b, ay0_c, ay1_a, ay1_b, ay1_c;
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wire [15:0] amp0_y, amp1_y;
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wire [7:0]ram_out, rom_out, latch_out;
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wire rom_enable = adr<16'h4000 ? 1:0;
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wire ram_enable = adr>=16'h4000 && adr<16'h4800 ? 1:0;
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wire latch_enable = adr==16'h6000 ? 1 : 0;
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wire ay_0_enable = adr==16'h8000 || adr==16'h8001 ? 1:0;
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wire ay_1_enable = adr==16'hC000 || adr==16'hC001 ? 1:0;
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assign bus_error = ~ram_enable & ~rom_enable & ~latch_enable &
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~ay_0_enable & ~ay_1_enable;
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assign cpu_in=ram_out | rom_out | latch_out;
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/*
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always @(negedge rd_n)
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if( !rd_n && adr==8'h38 )
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$display("IRQ processing started @ %t us",$time/1e6);
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*/
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initial begin
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nmi_n=1;
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wait_n=1;
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end
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tv80n cpu( //outputs
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.m1_n(m1_n), .mreq_n(mreq_n), .iorq_n(iorq_n), .rd_n(rd_n), .wr_n(wr_n),
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.rfsh_n(rfsh_n), .halt_n(halt_n), .busak_n(busak_n), .A(adr), .do(cpu_out),
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// Inputs
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.reset_n(reset_n), .clk(clk), .wait_n(wait_n),
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.int_n(int_n), .nmi_n(nmi_n), .busrq_n(busrq_n), .di(cpu_in) );
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RAM ram(.adr(adr[10:0]), .din(cpu_out), .dout(ram_out), .enable( ram_enable ),
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.clk(clk), .wr_n(wr_n), .rd_n(rd_n) );
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ROM rom(.adr(adr[13:0]), .data(rom_out), .enable(rom_enable),
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.rd_n(rd_n), .clk(clk));
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SOUND_LATCH sound_latch( .dout(latch_out), .enable(latch_enable),
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.clk(clk), .rd_n(rd_n) );
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// fake_ay ay_0( .adr(adr[0]), .din(din), .clk(clk), .wr_n(~ay_0_enable|wr_n) );
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AY_3_8910_capcom #(dump_regs,0) ay_0( .reset_n(reset_n), .clk(clk), .sound_clk(sound_clk),
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.din(cpu_out), .adr(adr[0]), .wr_n(wr_n), .cs_n(~ay_0_enable),
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.A(ay0_a), .B(ay0_b), .C(ay0_c) );
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AY_3_8910_capcom #(dump_regs,1) ay_1( .reset_n(reset_n), .clk(clk), .sound_clk(sound_clk),
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.din(cpu_out), .adr(adr[0]), .wr_n(wr_n), .cs_n(~ay_1_enable),
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.A(ay1_a), .B(ay1_b), .C(ay1_c) );
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endmodule
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//////////////////////////////////////////////////////////
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// this module is used to check the communication of the
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// Z80 with the AY-3-8910
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// only used for debugging
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module fake_ay(
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input adr,
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input [7:0] din,
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input clk,
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input wr_n );
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reg [7:0] contents[1:0];
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wire sample = clk & ~wr_n;
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always @(posedge sample) begin
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// if( contents[adr] != din ) begin
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$display("%t -> %d = %d", $realtime/1e6, adr, din );
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if( !adr && din>15 ) $display("AY WARNING");
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contents[adr] = din;
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end
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endmodule
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//////////////////////////////////////////////////////////
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module RAM(
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input [10:0] adr,
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input [7:0] din,
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output reg [7:0] dout,
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input enable,
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input clk,
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input rd_n,
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input wr_n );
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reg [7:0] contents[2047:0];
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wire sample = clk & (~rd_n | ~wr_n );
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initial dout=0;
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always @(posedge sample) begin
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if( !enable )
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dout=0;
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else begin
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if( !wr_n ) contents[adr]=din;
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if( !rd_n ) dout=contents[adr];
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end
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end
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endmodule
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//////////////////////////////////////////////////////////
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module ROM(
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input [13:0] adr,
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output reg [7:0] data,
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input enable,
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input rd_n,
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input clk );
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reg [7:0] contents[16383:0];
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wire sample = clk & ~rd_n;
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initial begin
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$readmemh("../rom/sr-01.c11.hex", contents ); // this is the hex dump of the ROM
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data=0;
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end
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always @( posedge sample ) begin
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if ( !enable )
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data=0;
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else
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data=contents[ adr ];
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end
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endmodule
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//////////////////////////////////////////////////////////
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module SOUND_LATCH(
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output reg [7:0] dout,
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input enable,
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input clk,
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input rd_n );
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wire sample = clk & ~rd_n;
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reg [7:0]data;
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initial begin
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dout=0;
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data=0;
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#100e6 data=8'h12; // enter the song/sound code here
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end
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always @(posedge sample) begin
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if( !enable )
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dout=0;
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else begin
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if( !rd_n ) begin
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// $display("Audio latch read @ %t us", $realtime/1e6 );
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// if( data != 0 )
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// $display("Audio latch read (%X) @ %t us", data, $realtime/1e6 );
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dout=data;
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end
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end
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end
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endmodule
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