/*
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/*
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SQmusic
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SQmusic
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(c) Jose Tejada Gomez, 9th May 2013
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(c) Jose Tejada Gomez, 9th May 2013
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You can use this file following the GNU GENERAL PUBLIC LICENSE version 3
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You can use this file following the GNU GENERAL PUBLIC LICENSE version 3
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Read the details of the license in:
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Read the details of the license in:
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http://www.gnu.org/licenses/gpl.txt
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http://www.gnu.org/licenses/gpl.txt
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Send comments to: jose.tejada@ieee.org
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Send comments to: jose.tejada@ieee.org
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*/
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*/
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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module sq_slot(
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module sq_slot(
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input clk,
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input clk,
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input reset_n,
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input reset_n,
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input [10:0] fnumber,
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input [10:0] fnumber,
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input [2:0] block,
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input [2:0] block,
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input [3:0] multiple
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input [3:0] multiple,
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output [12:0] linear
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);
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);
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wire [9:0]phase;
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wire [9:0]phase;
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wire [12:0] sin_log, sin_linear;
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wire [12:0] sin_log, sin_linear;
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sq_pg pg(
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sq_pg pg(
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.clk (clk),
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.clk (clk),
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.reset_n (reset_n),
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.reset_n (reset_n),
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.fnumber (fnumber),
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.fnumber (fnumber),
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.block (block),
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.block (block),
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.multiple(multiple),
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.multiple(multiple),
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.phase (phase) );
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.phase (phase) );
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sq_sin sin(
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sq_sin sin(
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.clk (clk),
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.clk (clk),
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.reset_n (reset_n),
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.reset_n (reset_n),
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.phase (phase),
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.phase (phase),
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.val (sin_log) );
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.val (sin_log) );
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sq_pow pow(
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sq_pow pow(
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.clk (clk),
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.clk (clk),
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.reset_n (reset_n),
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.reset_n (reset_n),
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.x (sin_log),
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.x (sin_log),
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.y (sin_linear) );
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.y (linear) );
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endmodule
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endmodule
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module sq_pg(
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module sq_pg(
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input clk,
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input clk,
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input reset_n,
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input reset_n,
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input [10:0] fnumber,
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input [10:0] fnumber,
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input [2:0] block,
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input [2:0] block,
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input [3:0] multiple,
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input [3:0] multiple,
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output [9:0]phase );
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output [9:0]phase );
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reg [19:0] count;
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reg [19:0] count;
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assign phase = count[19:10];
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assign phase = count[19:10];
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wire [19:0]fmult = fnumber << block;
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wire [19:0]fmult = fnumber << block;
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always @(posedge clk or negedge reset_n ) begin
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always @(posedge clk or negedge reset_n ) begin
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if( !reset_n )
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if( !reset_n )
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count <= 20'b0;
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count <= 20'b0;
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else begin
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else begin
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count <= count + ( multiple==4'b0 ? fmult>> 1 : fmult*multiple);
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count <= count + ( multiple==4'b0 ? fmult>> 1 : fmult*multiple);
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end
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end
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end
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end
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endmodule
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endmodule
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///////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////
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module sq_sin(
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module sq_sin(
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input clk,
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input clk,
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input reset_n,
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input reset_n,
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input [9:0]phase,
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input [9:0]phase,
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output [12:0] val // LSB is the sign. 0=positive, 1=negative
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output [12:0] val // LSB is the sign. 0=positive, 1=negative
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);
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);
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reg [12:0] sin_table[1023:0];
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reg [12:0] sin_table[1023:0];
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initial begin
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initial begin
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$readmemh("../tables/sin_table.hex", sin_table);
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$readmemh("../tables/sin_table.hex", sin_table);
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end
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end
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reg [9:0]last_phase;
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reg [9:0]last_phase;
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assign val = sin_table[last_phase];
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assign val = sin_table[last_phase];
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always @(posedge clk or negedge reset_n ) begin
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always @(posedge clk or negedge reset_n ) begin
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if( !reset_n )
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if( !reset_n )
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last_phase <= 10'b0;
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last_phase <= 10'b0;
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else begin
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else begin
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last_phase <= phase;
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last_phase <= phase;
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end
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end
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end
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end
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endmodule
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endmodule
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///////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////
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// sq_pow => reverse the log2 conversion
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// sq_pow => reverse the log2 conversion
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module sq_pow(
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module sq_pow(
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input clk,
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input clk,
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input reset_n,
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input reset_n,
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input [12:0]x,
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input rd_n, // read enable, active low
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output [12:0]y // LSB is the sign. 0=positive, 1=negative
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input [12:0]x, // LSB is the sign. 0=positive, 1=negative
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output reg [12:0]y
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);
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);
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parameter st_input = 3'b000;
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parameter st_lut_read = 3'b001;
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parameter st_shift = 3'b010;
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parameter st_sign = 3'b011;
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parameter st_output = 3'b100;
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reg [2:0] state;
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reg [12:0] pow_table[255:0];
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reg [12:0] pow_table[255:0];
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initial begin
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initial begin
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$readmemh("../tables/pow_table.hex", pow_table);
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$readmemh("../tables/pow_table.hex", pow_table);
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end
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end
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reg [7:0]index;
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reg [7:0]index;
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reg [2:0]exp;
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reg [3:0]exp;
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reg sign;
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reg sign;
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wire [12:0] raw = pow_table[index] >> exp;
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reg [12:0] raw, shifted, final;
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assign y = sign ? ~raw+13'b1 : raw; // regular 2's complement
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always @(posedge clk or negedge reset_n ) begin
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always @(posedge clk or negedge reset_n ) begin
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if( !reset_n ) begin
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if( !reset_n ) begin
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index <= 8'b0;
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index <= 8'b0;
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exp <= 3'b0;
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exp <= 3'b0;
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sign <= 1'b0;
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sign <= 1'b0;
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raw <= 13'b0;
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shifted <= 13'b0;
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y <= 12'b0;
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state <= st_input;
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end
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end
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else begin
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else begin
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exp <= x[12:10];
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case ( state )
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index <= x[9:1];
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st_input: begin
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if( !rd_n ) begin
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exp <= x[12:9];
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index <= x[8:1];
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sign <= x[0];
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sign <= x[0];
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state <= st_lut_read;
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end
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else state <= st_lut_read;
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end
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st_lut_read: begin
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raw <= pow_table[index];
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state <= st_shift;
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end
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st_shift: begin
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shifted <= raw >> exp;
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state <= st_sign;
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end
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st_sign: begin
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final <= sign ? ~shifted + 1'b1 : shifted;
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state <= st_output;
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end
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st_output: begin
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y <= final;
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state <= st_input;
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end
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endcase
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end
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end
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end
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end
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always @(posedge clk or negedge reset_n ) begin
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if( !reset_n )
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raw <= 13'b0;
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else
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raw <= pow_table[index];
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end
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always @(posedge clk or negedge reset_n ) begin
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if( !reset_n )
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shifted <= 13'b0;
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else
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shifted <= raw >> exp;
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end
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endmodule
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endmodule
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