/*
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/*
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SQmusic
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SQmusic
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logarithmic PWM controller to use with SQMUSIC
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logarithmic PWM controller to use with SQMUSIC
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Version 0.1, tested on simulation only with Capcom's 1942
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Version 0.1, tested on simulation only with Capcom's 1942
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(c) Jose Tejada Gomez, 11th May 2013
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(c) Jose Tejada Gomez, 11th May 2013
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You can use this file following the GNU GENERAL PUBLIC LICENSE version 3
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You can use this file following the GNU GENERAL PUBLIC LICENSE version 3
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Read the details of the license in:
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Read the details of the license in:
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http://www.gnu.org/licenses/gpl.txt
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http://www.gnu.org/licenses/gpl.txt
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Send comments to: jose.tejada@ieee.org
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Send comments to: jose.tejada@ieee.org
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*/
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*/
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module SQM_PWM(
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module SQM_PWM(
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input clk, // VHF clock (>33 MHz)
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input clk, // VHF clock (>33 MHz)
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input reset_n,
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input reset_n,
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input [3:0]A, input [3:0]B, input [3:0]C, // input channels
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input [3:0]A, input [3:0]B, input [3:0]C, // input channels
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output Y
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output Y
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);
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);
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SQM_PWM_1 apwm( .clk(clk), .reset_n(reset_n), .din(A), .pwm(y_a) );
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SQM_PWM_1 apwm( .clk(clk), .reset_n(reset_n), .din(A), .pwm(y_a) );
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SQM_PWM_1 bpwm( .clk(clk), .reset_n(reset_n), .din(B), .pwm(y_b) );
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SQM_PWM_1 bpwm( .clk(clk), .reset_n(reset_n), .din(B), .pwm(y_b) );
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SQM_PWM_1 cpwm( .clk(clk), .reset_n(reset_n), .din(C), .pwm(y_c) );
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SQM_PWM_1 cpwm( .clk(clk), .reset_n(reset_n), .din(C), .pwm(y_c) );
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assign Y=y_a | y_b | y_c;
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assign Y=y_a | y_b | y_c;
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endmodule
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endmodule
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////////////////////////////////////////////////////
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////////////////////////////////////////////////////
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// 1 channel only
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// 1 channel only
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module SQM_PWM_1(
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module SQM_PWM_1(
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input clk, // VHF clock (>33 MHz)
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input clk, // VHF clock (>33 MHz)
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input reset_n,
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input reset_n,
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input [3:0]din,
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input [3:0]din,
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output reg pwm
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output reg pwm
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);
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);
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reg [7:0] count, last0, last1;
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reg [7:0] count, last0, last1;
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wire [7:0]rep0, rep1;
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wire [7:0]rep0, rep1;
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SQM_PWM_LOG dec( .din(din), .rep0(rep0), .rep1(rep1), .zero(zero) );
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SQM_PWM_LOG dec( .din(din), .rep0(rep0), .rep1(rep1), .zero(zero) );
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always @(posedge clk or negedge reset_n) begin
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always @(posedge clk or negedge reset_n) begin
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if( !reset_n ) begin
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if( !reset_n ) begin
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count=0;
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count<=0;
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last0=0;
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last0<=0;
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last1=1;
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last1<=1;
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end
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end
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else
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else
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if( zero ) begin
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if( zero ) begin
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pwm=0;
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pwm <=0;
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count=0;
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count<=0;
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end
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end
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else if( last0!=rep0 || last1!=rep1 ) begin
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else if( last0!=rep0 || last1!=rep1 ) begin
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last0 <= rep0;
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last0 <= rep0;
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last1 <= rep1;
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last1 <= rep1;
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count = 0;
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count <= 0;
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pwm=0;
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pwm <=0;
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end
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end
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else if( last0==1 && last1==1 ) begin
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else if( last0==1 && last1==1 ) begin
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pwm=clk;
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pwm <=clk;
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count=0;
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count<=0;
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end
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end
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else begin
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else begin
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if( pwm && count==last1-1 ) begin
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if( pwm && count==last1-1 ) begin
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count=0;
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count<=0;
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pwm=0;
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pwm <=0;
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end
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end
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else if( !pwm && count==last0-1 ) begin
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else if( !pwm && count==last0-1 ) begin
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count=0;
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count<=0;
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pwm=1;
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pwm <=1;
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end
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end
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else begin
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else begin
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count<=count+1;
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count<=count+1;
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pwm<=pwm;
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pwm <=pwm;
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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module SQM_PWM_LOG(
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module SQM_PWM_LOG(
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input [3:0]din,
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input [3:0]din,
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output reg [7:0] rep0, // "L" repetition
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output reg [7:0] rep0, // "L" repetition
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output reg [7:0] rep1, // "H" repetition
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output reg [7:0] rep1, // "H" repetition
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output zero
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output zero
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);
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);
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assign zero = din==0;
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assign zero = din==0;
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always @(din)
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always @(din)
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case (din)
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case (din)
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1: begin
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1: begin
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rep0=64;
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rep0=64;
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rep1=1;
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rep1=1;
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end
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end
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2: begin
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2: begin
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rep0=61;
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rep0=61;
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rep1=1;
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rep1=1;
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end
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end
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3: begin
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3: begin
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rep0=32;
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rep0=32;
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rep1=1;
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rep1=1;
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end
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end
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4: begin
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4: begin
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rep0=61;
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rep0=61;
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rep1=2;
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rep1=2;
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end
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end
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5: begin
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5: begin
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rep0=16;
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rep0=16;
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rep1=1;
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rep1=1;
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end
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end
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6: begin
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6: begin
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rep0=61;
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rep0=61;
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rep1=4;
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rep1=4;
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end
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end
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7: begin
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7: begin
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rep0=8;
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rep0=8;
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rep1=1;
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rep1=1;
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end
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end
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8: begin
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8: begin
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rep0=61;
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rep0=61;
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rep1=8;
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rep1=8;
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end
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end
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9: begin
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9: begin
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rep0=61;
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rep0=61;
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rep1=16;
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rep1=16;
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end
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end
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10: begin
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10: begin
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rep0=61;
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rep0=61;
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rep1=8;
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rep1=8;
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end
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end
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11: begin
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11: begin
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rep0=2;
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rep0=2;
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rep1=1;
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rep1=1;
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end
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end
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12: begin
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12: begin
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rep0=61;
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rep0=61;
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rep1=32;
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rep1=32;
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end
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end
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13: begin
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13: begin
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rep0=1;
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rep0=1;
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rep1=1;
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rep1=1;
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end
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end
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14: begin
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14: begin
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rep0=61;
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rep0=61;
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rep1=64;
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rep1=64;
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end
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end
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15: begin
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15: begin
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rep0=1;
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rep0=1;
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rep1=1;
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rep1=1;
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end
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end
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default: begin
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default: begin
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rep0=1;
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rep0=1;
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rep1=1;
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rep1=1;
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end
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end
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endcase
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endcase
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endmodule
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endmodule
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