/*
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/*
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SQmusic
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SQmusic
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Music synthetiser compatible with AY-3-8910 software compatible
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Music synthetiser compatible with AY-3-8910 software compatible
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Version 0.1, tested on simulation only with Capcom's 1942
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Version 0.1, tested on simulation only with Capcom's 1942
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(c) Jose Tejada Gomez, 9th May 2013
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(c) Jose Tejada Gomez, 9th May 2013
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You can use this file following the GNU GENERAL PUBLIC LICENSE version 3
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You can use this file following the GNU GENERAL PUBLIC LICENSE version 3
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Read the details of the license in:
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Read the details of the license in:
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http://www.gnu.org/licenses/gpl.txt
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http://www.gnu.org/licenses/gpl.txt
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Send comments to: jose.tejada@ieee.org
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Send comments to: jose.tejada@ieee.org
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*/
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*/
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/* Capcom arcade boards like 1942 use two memory locations to
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/* Capcom arcade boards like 1942 use two memory locations to
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communicate with the AY-3-8910 (or compatible) chip. This small code
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communicate with the AY-3-8910 (or compatible) chip. This small code
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provides a 2-byte memory map as expected by Capcom games
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provides a 2-byte memory map as expected by Capcom games
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*/
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*/
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module AY_3_8910_capcom
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module AY_3_8910_capcom
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#( parameter dump_writes=0, parameter id=0 )
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#( parameter dump_writes=0, parameter id=0 )
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(
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(
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input reset_n,
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input reset_n,
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input clk, // CPU clock
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input clk, // CPU clock
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input sound_clk, // normally slower than the CPU clock
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input sound_clk, // normally slower than the CPU clock
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input [7:0] din,
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input [7:0] din,
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input adr,
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input adr,
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input wr_n, // write
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input wr_n, // write
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input cs_n, // chip select
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input cs_n, // chip select
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output [3:0]A,B,C // channel outputs
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output [3:0]A,B,C // channel outputs
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);
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);
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reg [7:0] latches[1:0];
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reg [3:0] adr_latch;
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reg core_wr;
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wire sample = ~cs_n & ~wr_n;
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wire sample = clk & ~cs_n & ~wr_n;
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wire core_wr = adr & sample;
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reg count;
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reg count;
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always @(posedge sound_clk or negedge reset_n) begin
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always @(posedge clk or negedge reset_n) begin
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if(!reset_n) begin
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if(!reset_n)
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count=0;
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adr_latch <= 0;
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end
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else
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else begin
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if( sample && adr==0 )
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if( !count && core_wr) count=1;
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adr_latch <= din[3:0];
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else if( core_wr ) begin
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count=0;
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core_wr=0;
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end
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end
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end
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always @(posedge sample or negedge reset_n) begin
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if(!reset_n) begin
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latches[0]=0;
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latches[1]=0;
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end
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else begin
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latches[adr] = din;
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if(adr) core_wr=1;
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end
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end
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end
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SQMUSIC #(dump_writes, id) core( .reset_n(reset_n), .clk(sound_clk), .data_in(latches[1]),
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SQMUSIC #(dump_writes, id) core( .reset_n(reset_n), .clk(sound_clk), .data_in(din),
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.adr( latches[0][3:0] ), .rd(1'b0), .wr(core_wr), .A(A), .B(B), .C(C) );
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.adr( adr_latch ), .rd(1'b0), .wr(core_wr), .A(A), .B(B), .C(C) );
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endmodule
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endmodule
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//////////////////////////////////////////////////////////////////////////////
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/* The AY core does
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/* The AY core does
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*/
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*/
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module SQMUSIC
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module SQMUSIC
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#( parameter dump_writes=0, parameter id=0 ) // set to 1 to dump register writes
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#( parameter dump_writes=0, parameter id=0 ) // set to 1 to dump register writes
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( // note that input ports are not multiplexed
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( // note that input ports are not multiplexed
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input reset_n,
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input reset_n,
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input clk,
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input clk,
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input [7:0] data_in,
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input [7:0] data_in,
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output reg [7:0] data_out,
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output reg [7:0] data_out,
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input [3:0] adr,
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input [3:0] adr,
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input rd, // read
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input rd, // read
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input wr, // write
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input wr, // write
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output [3:0]A,B,C // channel outputs
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output [3:0]A,B,C // channel outputs
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);
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);
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reg [7:0] regarray[15:0];
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reg [7:0] regarray[15:0];
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reg [3:0] clkdiv16;
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reg [3:0] clkdiv16;
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wire [3:0] envelope;
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wire [3:0] envelope;
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wire [2:0] sqwave;
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wire [2:0] sqwave;
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wire noise, envclk;
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wire noise, envclk;
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wire Amix = (noise|regarray[7][3]) ^ (sqwave[0]|regarray[7][0]);
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wire Amix = (noise|regarray[7][3]) ^ (sqwave[0]|regarray[7][0]);
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wire Bmix = (noise|regarray[7][4]) ^ (sqwave[1]|regarray[7][1]);
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wire Bmix = (noise|regarray[7][4]) ^ (sqwave[1]|regarray[7][1]);
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wire Cmix = (noise|regarray[7][5]) ^ (sqwave[2]|regarray[7][2]);
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wire Cmix = (noise|regarray[7][5]) ^ (sqwave[2]|regarray[7][2]);
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// internal modules operate at clk/16
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// internal modules operate at clk/16
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SQM_CLK_DIVIDER #(12) chA( .clk(clkdiv16[3]), .reset_n(reset_n),
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SQM_CLK_DIVIDER #(12) chA( .clk(clkdiv16[3]), .reset_n(reset_n),
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.period({regarray[1][3:0], regarray[0][7:0] }), .div(sqwave[0]) );
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.period({regarray[1][3:0], regarray[0][7:0] }), .div(sqwave[0]) );
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SQM_CLK_DIVIDER #(12) chB( .clk(clkdiv16[3]), .reset_n(reset_n),
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SQM_CLK_DIVIDER #(12) chB( .clk(clkdiv16[3]), .reset_n(reset_n),
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.period({regarray[3][3:0], regarray[2][7:0] }), .div(sqwave[1]) );
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.period({regarray[3][3:0], regarray[2][7:0] }), .div(sqwave[1]) );
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SQM_CLK_DIVIDER #(12) chC( .clk(clkdiv16[3]), .reset_n(reset_n),
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SQM_CLK_DIVIDER #(12) chC( .clk(clkdiv16[3]), .reset_n(reset_n),
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.period({regarray[5][3:0], regarray[4][7:0] }), .div(sqwave[2]) );
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.period({regarray[5][3:0], regarray[4][7:0] }), .div(sqwave[2]) );
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// the noise uses a x2 faster clock in order to produce a frequency
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// the noise uses a x2 faster clock in order to produce a frequency
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// of Fclk/16 when period is 1
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// of Fclk/16 when period is 1
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SQM_NOISE ng( .clk(clkdiv16[3]), .reset_n(reset_n),
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SQM_NOISE ng( .clk(clkdiv16[3]), .reset_n(reset_n),
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.period(regarray[6][4:0]), .noise(noise) );
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.period(regarray[6][4:0]), .noise(noise) );
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// envelope generator
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// envelope generator
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SQM_CLK_DIVIDER #(16) envclkdiv( .clk(clkdiv16[2]), .reset_n(reset_n),
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SQM_CLK_DIVIDER #(16) envclkdiv( .clk(clkdiv16[2]), .reset_n(reset_n),
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.period({regarray[14],regarray[13]}), .div(envclk) );
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.period({regarray[14],regarray[13]}), .div(envclk) );
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SQM_ENVELOPE env( .clk(envclk),.ctrl(regarray[15][3:0]),
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SQM_ENVELOPE env( .clk(envclk),.ctrl(regarray[15][3:0]),
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.gain(envelope), .reset_n(reset_n) );
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.gain(envelope), .reset_n(reset_n) );
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assign A=regarray[10][4]? envelope&{4{Amix}} : regarray[10][3:0]&{4{Amix}};
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assign A=regarray[10][4]? envelope&{4{Amix}} : regarray[10][3:0]&{4{Amix}};
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assign B=regarray[11][4]? envelope&{4{Bmix}} : regarray[10][3:0]&{4{Bmix}};
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assign B=regarray[11][4]? envelope&{4{Bmix}} : regarray[10][3:0]&{4{Bmix}};
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assign C=regarray[12][4]? envelope&{4{Cmix}} : regarray[10][3:0]&{4{Cmix}};
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assign C=regarray[12][4]? envelope&{4{Cmix}} : regarray[10][3:0]&{4{Cmix}};
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integer aux;
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// 16-count divider
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// 16-count divider
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always @(posedge clk or reset_n) begin
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always @(posedge clk or negedge reset_n) begin
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if( !reset_n)
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if( !reset_n)
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clkdiv16=0;
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clkdiv16<=0;
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else
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else
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clkdiv16<=clkdiv16+1;
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clkdiv16<=clkdiv16+1;
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end
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end
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always @(posedge clk or reset_n) begin
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integer aux;
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always @(posedge clk or negedge reset_n) begin
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if( !reset_n ) begin
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if( !reset_n ) begin
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data_out=0;
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data_out=0;
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for(aux=0;aux<=15;aux=aux+1) regarray[aux]=0;
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for(aux=0;aux<=15;aux=aux+1) regarray[aux]=0;
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end
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end
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else begin
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else begin
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if( rd )
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if( rd )
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data_out=regarray[ adr ];
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data_out=regarray[ adr ];
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else if( wr ) begin
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else if( wr ) begin
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regarray[adr]=data_in;
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regarray[adr]=data_in;
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if( dump_writes ) begin
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if( dump_writes ) begin
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$display("#%d, %t, %d, %d", id, $realtime, adr, data_in );
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$display("#%d, %t, %d, %d", id, $realtime, adr, data_in );
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end
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end
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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module SQM_CLK_DIVIDER(
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module SQM_CLK_DIVIDER(
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clk, // this is the divided down clock from the core
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clk, // this is the divided down clock from the core
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reset_n,
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reset_n,
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period,
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period,
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div
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div
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);
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);
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parameter bw=12;
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parameter bw=12;
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input clk; // this is the divided down clock from the core
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input clk; // this is the divided down clock from the core
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input reset_n;
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input reset_n;
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input [bw-1:0]period;
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input [bw-1:0]period;
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output div;
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output div;
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reg [bw-1:0]count;
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reg [bw-1:0]count;
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reg clkdiv;
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reg clkdiv;
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initial clkdiv=0;
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initial clkdiv=0;
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assign div = period==1 ? clk : clkdiv;
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assign div = period==1 ? clk : clkdiv;
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always @(posedge clk or reset_n) begin
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always @(posedge clk or negedge reset_n) begin
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if( !reset_n) begin
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if( !reset_n) begin
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count=0;
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count<=0;
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clkdiv=0;
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clkdiv<=0;
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end
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end
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else begin
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else begin
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if( period==0 ) begin
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if( period==0 ) begin
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clkdiv<=0;
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clkdiv<=0;
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count<=0;
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count<=0;
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end
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end
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else if( count >= period ) begin
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else if( count >= period ) begin
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count <= 0;
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count <= 0;
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clkdiv = ~clkdiv;
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clkdiv <= ~clkdiv;
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end
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end
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else count <= count+1;
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else count <= count+1;
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end
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end
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end
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end
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endmodule
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endmodule
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////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////
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module SQM_NOISE(
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module SQM_NOISE(
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input clk, // this is the divided down clock from the core
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input clk, // this is the divided down clock from the core
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input reset_n,
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input reset_n,
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input [4:0]period,
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input [4:0]period,
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output noise
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output noise
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);
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);
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reg [5:0]count;
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reg [5:0]count;
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reg [16:0]poly17;
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reg [16:0]poly17;
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wire poly17_zero = poly17==0;
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wire poly17_zero = poly17==0;
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assign noise=poly17[16];
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assign noise=poly17[16];
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wire noise_clk;
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wire noise_clk;
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always @(posedge noise_clk or reset_n) begin
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always @(posedge noise_clk or negedge reset_n) begin
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if( !reset_n) begin
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if( !reset_n) begin
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poly17=0;
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poly17<=0;
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end
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end
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else begin
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else begin
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poly17={ poly17[0] ^ poly17[2] ^ poly17_zero, poly17[16:1] };
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poly17<={ poly17[0] ^ poly17[2] ^ poly17_zero, poly17[16:1] };
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end
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end
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end
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end
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SQM_CLK_DIVIDER #(5) ndiv( .clk(clk), .reset_n(reset_n),
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SQM_CLK_DIVIDER #(5) ndiv( .clk(clk), .reset_n(reset_n),
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.period(period), .div(noise_clk) );
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.period(period), .div(noise_clk) );
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endmodule
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endmodule
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////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////
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module SQM_ENVELOPE(
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module SQM_ENVELOPE(
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input clk, // this is the divided down clock from the core
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input clk, // this is the divided down clock from the core
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input reset_n,
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input reset_n,
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input [3:0]ctrl,
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input [3:0]ctrl,
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output reg [3:0]gain
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output reg [3:0]gain
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);
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);
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reg dir; // direction
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reg dir; // direction
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reg stop;
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reg stop;
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reg [3:0]prev_ctrl; // last control orders
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reg [3:0]prev_ctrl; // last control orders
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always @(posedge clk or reset_n) begin
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always @(posedge clk or negedge reset_n) begin
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if( !reset_n) begin
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if( !reset_n) begin
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gain=4'hF;
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gain<=4'hF;
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dir=0;
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dir<=0;
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prev_ctrl=0;
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prev_ctrl<=0;
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stop=1;
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stop<=1;
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end
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end
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else begin
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else begin
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if (ctrl!=prev_ctrl) begin
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if (ctrl!=prev_ctrl) begin
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prev_ctrl<=ctrl;
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prev_ctrl<=ctrl;
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if( ctrl[2] ) begin
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if( ctrl[2] ) begin
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gain<=0;
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gain<=0;
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dir<=1;
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dir<=1;
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stop<=0;
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stop<=0;
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end
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end
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else begin
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else begin
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gain<=4'hF;
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gain<=4'hF;
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dir<=0;
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dir<=0;
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stop<=0;
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stop<=0;
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end
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end
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end
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end
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else begin
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else begin
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if (!stop) begin
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if (!stop) begin
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if( !prev_ctrl[3] && ((gain==0&&!dir) || (gain==4'hF&&dir))) begin
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if( !prev_ctrl[3] && ((gain==0&&!dir) || (gain==4'hF&&dir))) begin
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stop<=1;
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stop<=1;
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gain<=0;
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gain<=0;
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end
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end
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else begin
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else begin
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if( prev_ctrl[0] && ( (gain==0&&!dir) || (gain==4'hF&&dir))) begin // HOLD
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if( prev_ctrl[0] && ( (gain==0&&!dir) || (gain==4'hF&&dir))) begin // HOLD
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stop<=1;
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stop<=1;
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gain <= prev_ctrl[1]? ~gain : gain;
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gain <= prev_ctrl[1]? ~gain : gain;
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end
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end
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else begin
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else begin
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gain <= dir ? gain+1 : gain-1;
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gain <= dir ? gain+1 : gain-1;
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if( prev_ctrl[1:0]==2'b10 && ( (gain==1&&!dir) || (gain==4'hE&&dir))) begin // ALTERNATE
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if( prev_ctrl[1:0]==2'b10 && ( (gain==1&&!dir) || (gain==4'hE&&dir))) begin // ALTERNATE
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dir <= ~dir;
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dir <= ~dir;
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end
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end
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end
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end
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end
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end
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end
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end
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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