`timescale 1ns/1ns
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`timescale 1ns/1ns
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module bench_fifo_s;
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module bench_fifo_s;
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reg clk, reset;
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reg clk, reset;
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localparam width = 8;
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localparam width = 8;
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initial clk = 0;
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initial clk = 0;
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always #10 clk = ~clk;
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always #10 clk = ~clk;
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [width-1:0] chk_data; // From fifo_s of sd_fifo_s.v
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wire [width-1:0] chk_data; // From fifo_s of sd_fifo_s.v
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wire chk_drdy; // From chk of sd_seq_check.v
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wire chk_drdy; // From chk of sd_seq_check.v
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wire chk_srdy; // From fifo_s of sd_fifo_s.v
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wire chk_srdy; // From fifo_s of sd_fifo_s.v
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wire [width-1:0] gen_data; // From gen of sd_seq_gen.v
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wire [width-1:0] gen_data; // From gen of sd_seq_gen.v
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wire gen_drdy; // From fifo_s of sd_fifo_s.v
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wire gen_drdy; // From fifo_s of sd_fifo_s.v
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wire gen_srdy; // From gen of sd_seq_gen.v
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wire gen_srdy; // From gen of sd_seq_gen.v
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// End of automatics
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// End of automatics
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/* sd_seq_gen AUTO_TEMPLATE
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/* sd_seq_gen AUTO_TEMPLATE
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(
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(
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.p_\(.*\) (gen_\1[]),
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.p_\(.*\) (gen_\1[]),
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);
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);
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*/
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*/
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sd_seq_gen gen
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sd_seq_gen gen
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.p_srdy (gen_srdy), // Templated
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.p_srdy (gen_srdy), // Templated
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.p_data (gen_data[width-1:0]), // Templated
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.p_data (gen_data[width-1:0]), // Templated
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.p_drdy (gen_drdy)); // Templated
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.p_drdy (gen_drdy)); // Templated
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/* sd_seq_check AUTO_TEMPLATE
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/* sd_seq_check AUTO_TEMPLATE
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(
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(
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.c_\(.*\) (chk_\1[]),
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.c_\(.*\) (chk_\1[]),
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);
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);
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*/
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*/
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sd_seq_check chk
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sd_seq_check chk
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.c_drdy (chk_drdy), // Templated
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.c_drdy (chk_drdy), // Templated
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.c_srdy (chk_srdy), // Templated
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.c_srdy (chk_srdy), // Templated
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.c_data (chk_data[width-1:0])); // Templated
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.c_data (chk_data[width-1:0])); // Templated
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/* sd_fifo_s AUTO_TEMPLATE
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/* sd_fifo_s AUTO_TEMPLATE
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(
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(
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.c_clk (clk),
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.c_clk (clk),
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.c_reset (reset),
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.c_reset (reset),
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.p_clk (clk),
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.p_clk (clk),
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.p_reset (reset),
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.p_reset (reset),
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.p_\(.*\) (chk_\1[]),
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.p_\(.*\) (chk_\1[]),
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.c_\(.*\) (gen_\1[]),
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.c_\(.*\) (gen_\1[]),
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);
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);
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*/
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*/
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sd_fifo_s #(8, 32, 1) fifo_s
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sd_fifo_s #(8, 32, 1) fifo_s
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.c_drdy (gen_drdy), // Templated
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.c_drdy (gen_drdy), // Templated
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.p_srdy (chk_srdy), // Templated
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.p_srdy (chk_srdy), // Templated
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.p_data (chk_data[width-1:0]), // Templated
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.p_data (chk_data[width-1:0]), // Templated
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// Inputs
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// Inputs
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.c_clk (clk), // Templated
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.c_clk (clk), // Templated
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.c_reset (reset), // Templated
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.c_reset (reset), // Templated
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.c_srdy (gen_srdy), // Templated
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.c_srdy (gen_srdy), // Templated
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.c_data (gen_data[width-1:0]), // Templated
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.c_data (gen_data[width-1:0]), // Templated
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.p_clk (clk), // Templated
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.p_clk (clk), // Templated
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.p_reset (reset), // Templated
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.p_reset (reset), // Templated
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.p_drdy (chk_drdy)); // Templated
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.p_drdy (chk_drdy)); // Templated
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initial
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initial
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begin
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begin
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$dumpfile("fifo_s.vcd");
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$dumpfile("fifo_s.vcd");
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$dumpvars;
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$dumpvars;
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reset = 1;
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reset = 1;
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#100;
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#100;
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reset = 0;
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reset = 0;
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gen.rep_count = 1000;
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// burst normal data for 20 cycles
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// burst normal data for 20 cycles
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repeat (20) @(posedge clk);
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repeat (20) @(posedge clk);
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gen.srdy_pat = 8'h5A;
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gen.srdy_pat = 8'h5A;
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repeat (20) @(posedge clk);
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repeat (20) @(posedge clk);
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chk.drdy_pat = 8'hA5;
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chk.drdy_pat = 8'hA5;
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repeat (40) @(posedge clk);
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repeat (40) @(posedge clk);
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// check FIFO overflow
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// check FIFO overflow
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gen.srdy_pat = 8'hFD;
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gen.srdy_pat = 8'hFD;
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repeat (100) @(posedge clk);
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repeat (100) @(posedge clk);
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// check FIFO underflow
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// check FIFO underflow
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gen.srdy_pat = 8'h11;
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gen.srdy_pat = 8'h11;
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repeat (100) @(posedge clk);
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repeat (100) @(posedge clk);
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#5000;
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#5000;
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$finish;
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$finish;
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end
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end
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endmodule // bench_fifo_s
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endmodule // bench_fifo_s
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// Local Variables:
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// Local Variables:
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// verilog-library-directories:("." "../../rtl/verilog/buffers")
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// verilog-library-directories:("." "../../rtl/verilog/buffers")
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// End:
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// End:
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