module concentrator
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module concentrator
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(input clk,
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(input clk,
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input reset,
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input reset,
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input [7:0] c_data,
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input [7:0] c_data,
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input [1:0] c_code,
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input [1:0] c_code,
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input c_srdy, // To sdin of sd_input.v
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input c_srdy, // To sdin of sd_input.v
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input p_drdy, // To sdout of sd_output.v
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input p_drdy, // To sdout of sd_output.v
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output c_drdy, // From sdin of sd_input.v
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output c_drdy, // From sdin of sd_input.v
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output reg [`PFW_SZ-1:0] p_data, // From sdout of sd_output.v
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output reg [`PFW_SZ-1:0] p_data, // From sdout of sd_output.v
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output reg p_srdy,
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output reg p_srdy,
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output reg p_commit,
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output reg p_commit,
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output reg p_abort
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output reg p_abort
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// End of automatics
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// End of automatics
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);
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);
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wire [`PFW_SZ-1:0] ic_data; // From body of template_body_1i1o.v
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wire ic_drdy; // From sdout of sd_output.v
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wire ic_srdy; // From body of template_body_1i1o.v
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wire [7:0] ip_data; // From sdin of sd_input.v
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wire [7:0] ip_data; // From sdin of sd_input.v
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wire [1:0] ip_code;
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wire [1:0] ip_code;
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reg ip_drdy;
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reg ip_drdy;
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wire ip_srdy; // From sdin of sd_input.v
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wire ip_srdy; // From sdin of sd_input.v
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reg [`PFW_SZ-1:0] nxt_p_data;
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reg [`PFW_SZ-1:0] nxt_p_data;
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reg [1:0] nxt_pkt_code, pkt_code;
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reg nxt_p_srdy;
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reg nxt_p_srdy;
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reg [2:0] count, nxt_count;
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reg [2:0] count, nxt_count;
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reg nxt_p_abort, nxt_p_commit;
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reg nxt_p_abort, nxt_p_commit;
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wire [1:0] pkt_code = p_data[`PRW_PCC];
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sd_input #(8+2) sdin
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sd_input #(8+2) sdin
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(
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(
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// Outputs
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// Outputs
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.c_drdy (c_drdy),
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.c_drdy (c_drdy),
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.ip_srdy (ip_srdy),
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.ip_srdy (ip_srdy),
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.ip_data ({ip_code,ip_data}),
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.ip_data ({ip_code,ip_data}),
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.c_srdy (c_srdy),
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.c_srdy (c_srdy),
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.c_data ({c_code,c_data}),
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.c_data ({c_code,c_data}),
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.ip_drdy (ip_drdy));
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.ip_drdy (ip_drdy));
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always @*
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always @*
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begin
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begin
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nxt_p_data = p_data;
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nxt_p_data = p_data;
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nxt_p_srdy = p_srdy;
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nxt_p_srdy = p_srdy;
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nxt_pkt_code = pkt_code;
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nxt_p_data = p_data;
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nxt_p_data = p_data;
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nxt_count = count;
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nxt_count = count;
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nxt_p_commit = p_commit;
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nxt_p_commit = p_commit;
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nxt_p_abort = 0;
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nxt_p_abort = 0;
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if (p_srdy)
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if (p_srdy)
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begin
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begin
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if (p_drdy)
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if (p_drdy)
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begin
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begin
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nxt_p_srdy = 0;
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nxt_p_srdy = 0;
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nxt_p_commit = 0;
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nxt_p_commit = 0;
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ip_drdy = 1;
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ip_drdy = 1;
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nxt_pkt_code = `PCC_DATA;
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nxt_p_data[`PRW_PCC] = `PCC_DATA;
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nxt_count = 0;
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nxt_count = 0;
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if (ip_srdy)
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if (ip_srdy)
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begin
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begin
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nxt_count = 1;
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nxt_count = 1;
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if (ip_code != `PCC_DATA)
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if (ip_code != `PCC_DATA)
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nxt_pkt_code = ip_code;
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nxt_p_data[`PRW_PCC] = ip_code;
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nxt_p_data[63:56] = ip_data;
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nxt_p_data[63:56] = ip_data;
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end
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end
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end
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end
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end
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end
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else if (ip_srdy)
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else if (ip_srdy)
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begin
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begin
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ip_drdy = 1;
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ip_drdy = 1;
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if (ip_code != `PCC_DATA)
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if (ip_code != `PCC_DATA)
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nxt_pkt_code = ip_code;
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nxt_p_data[`PRW_PCC] = ip_code;
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nxt_count = count + 1;
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nxt_count = count + 1;
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case (count)
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case (count)
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0 : nxt_p_data[63:56] = ip_data;
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0 : nxt_p_data[63:56] = ip_data;
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1 : nxt_p_data[55:48] = ip_data;
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1 : nxt_p_data[55:48] = ip_data;
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2 : nxt_p_data[47:40] = ip_data;
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2 : nxt_p_data[47:40] = ip_data;
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3 : nxt_p_data[39:32] = ip_data;
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3 : nxt_p_data[39:32] = ip_data;
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4 : nxt_p_data[31:24] = ip_data;
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4 : nxt_p_data[31:24] = ip_data;
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5 : nxt_p_data[23:16] = ip_data;
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5 : nxt_p_data[23:16] = ip_data;
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6 : nxt_p_data[15: 8] = ip_data;
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6 : nxt_p_data[15: 8] = ip_data;
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7 : nxt_p_data[ 7: 0] = ip_data;
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7 : nxt_p_data[ 7: 0] = ip_data;
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endcase // case (count)
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endcase // case (count)
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if ((count == 7) | (ip_code == `PCC_BADEOP) | (ip_code == `PCC_EOP))
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if ((count == 7) | (ip_code == `PCC_BADEOP) | (ip_code == `PCC_EOP))
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begin
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begin
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if (ip_code == `PCC_EOP)
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if (ip_code == `PCC_EOP)
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begin
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begin
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nxt_p_commit = 1;
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nxt_p_commit = 1;
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nxt_p_srdy = 1;
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nxt_p_srdy = 1;
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nxt_p_data[`PRW_VALID] = count + 1;
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end
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end
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else if ((ip_code == `PCC_BADEOP) || (pkt_code == `PCC_BADEOP))
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else if ((ip_code == `PCC_BADEOP) || (pkt_code == `PCC_BADEOP))
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begin
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begin
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nxt_p_abort = 1;
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nxt_p_abort = 1;
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end
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end
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else
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else
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begin
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nxt_p_srdy = 1;
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nxt_p_srdy = 1;
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nxt_p_data[`PRW_VALID] = 0;
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end
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end
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end
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end
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end
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end // always @ *
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end // always @ *
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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count <= 3'h0;
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count <= 3'h0;
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p_abort <= 1'h0;
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p_abort <= 1'h0;
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p_commit <= 1'h0;
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p_commit <= 1'h0;
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p_data <= {(1+(`PFW_SZ-1)){1'b0}};
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p_data <= {(1+(`PFW_SZ-1)){1'b0}};
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p_srdy <= 1'h0;
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p_srdy <= 1'h0;
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// End of automatics
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// End of automatics
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end
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end
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else
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else
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begin
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begin
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p_commit <= #1 nxt_p_commit;
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p_commit <= #1 nxt_p_commit;
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p_abort <= #1 nxt_p_abort;
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p_abort <= #1 nxt_p_abort;
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p_srdy <= #1 nxt_p_srdy;
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p_srdy <= #1 nxt_p_srdy;
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p_data <= #1 nxt_p_data;
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p_data <= #1 nxt_p_data;
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count <= #1 nxt_count;
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count <= #1 nxt_count;
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end // else: !if(reset)
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end // else: !if(reset)
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end
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end
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endmodule // template_1i1o
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endmodule // template_1i1o
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