module distributor
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module distributor
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#(parameter width=8)
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(input clk,
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(input clk,
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input reset,
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input reset,
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input ptx_srdy,
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input ptx_srdy,
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output ptx_drdy,
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output ptx_drdy,
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input [`PFW_SZ-1:0] ptx_data,
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input [`PFW_SZ-1:0] ptx_data,
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output p_srdy,
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output p_srdy,
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input p_drdy,
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input p_drdy,
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output [1:0] p_code,
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output [1:0] p_code,
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output [7:0] p_data
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output [7:0] p_data
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);
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);
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wire [width-1:0] ic_data; // From body of template_body_1i1o.v
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reg [7:0] ic_data;
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wire ic_drdy; // From sdout of sd_output.v
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reg [1:0] ic_code;
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wire ic_srdy; // From body of template_body_1i1o.v
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wire ic_drdy;
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wire [width-1:0] ip_data; // From sdin of sd_input.v
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reg ic_srdy;
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wire ip_drdy; // From body of template_body_1i1o.v
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wire [`PFW_SZ-1:0] ip_data;
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wire ip_srdy; // From sdin of sd_input.v
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reg ip_drdy;
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// End of automatics
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wire ip_srdy;
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reg [7:0] remain, nxt_remain;
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sd_input #(width) sdin
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sd_input #(`PFW_SZ) sdin
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(/*AUTOINST*/
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(
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// Outputs
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// Outputs
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.c_drdy (c_drdy),
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.c_drdy (ptx_drdy),
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.ip_srdy (ip_srdy),
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.ip_srdy (ip_srdy),
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.ip_data (ip_data[width-1:0]),
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.ip_data (ip_data),
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.c_srdy (c_srdy),
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.c_srdy (ptx_srdy),
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.c_data (c_data[width-1:0]),
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.c_data (ptx_data),
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.ip_drdy (ip_drdy));
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.ip_drdy (ip_drdy));
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template_body_1i1o #(width) body
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always @*
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(/*AUTOINST*/
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begin
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// Outputs
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nxt_remain = remain;
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.ic_data (ic_data[width-1:0]),
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ic_srdy = 0;
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.ic_srdy (ic_srdy),
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ip_drdy = 0;
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.ip_drdy (ip_drdy),
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// Inputs
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.clk (clk),
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.reset (reset),
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.ic_drdy (ic_drdy),
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.ip_data (ip_data[width-1:0]),
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.ip_srdy (ip_srdy));
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sd_output #(width) sdout
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case (remain)
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(/*AUTOINST*/
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0 : ic_data = ip_data[63:56];
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// Outputs
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7 : ic_data = ip_data[55:48];
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.ic_drdy (ic_drdy),
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6 : ic_data = ip_data[47:40];
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.p_srdy (p_srdy),
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5 : ic_data = ip_data[39:32];
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.p_data (p_data[width-1:0]),
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4 : ic_data = ip_data[31:24];
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// Inputs
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3 : ic_data = ip_data[23:16];
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.clk (clk),
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2 : ic_data = ip_data[15: 8];
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.reset (reset),
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1 : ic_data = ip_data[ 7: 0];
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.ic_srdy (ic_srdy),
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default : ic_data = ip_data[63:56];
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.ic_data (ic_data[width-1:0]),
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endcase
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.p_drdy (p_drdy));
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endmodule // template_1i1o
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if (ip_srdy & ic_drdy)
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begin
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if (remain == 0)
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begin
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ic_srdy = 1;
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if (ip_data[`PRW_VALID] == 0)
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nxt_remain = 7;
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else
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nxt_remain = ip_data[`PRW_VALID]-1;
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module template_body_1i1o
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if (nxt_remain == 0)
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#(parameter width=8)
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ip_drdy = 1;
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(input clk,
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input reset,
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output reg [width-1:0] ic_data,
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output reg ic_srdy,
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output reg ip_drdy,
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input ic_drdy,
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input [width-1:0] ip_data,
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input ip_srdy
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);
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always @*
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if (ip_data[`PRW_PCC] == `PCC_SOP)
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begin
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ic_code = `PCC_SOP;
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ic_data = ip_data;
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else
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if (ip_srdy & ip_drdy)
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ic_code = `PCC_DATA;
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end // if (remain == 0)
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else
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begin
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begin
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ic_srdy = 1;
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ic_srdy = 1;
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nxt_remain = remain - 1;
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if (nxt_remain == 0)
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begin
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ip_drdy = 1;
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ip_drdy = 1;
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if ((ip_data[`PRW_PCC] == `PCC_EOP) |
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(ip_data[`PRW_PCC] == `PCC_BADEOP))
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ic_code = ip_data[`PRW_PCC];
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else
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ic_code = `PCC_DATA;
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end
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end
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else
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else
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begin
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ic_code = `PCC_DATA;
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ic_srdy = 0;
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end // else: !if(remain == 0)
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ip_drdy = 0;
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end
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end
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end // always @ *
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always @(posedge clk)
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begin
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if (reset)
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remain <= #1 0;
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else
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remain <= #1 nxt_remain;
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end
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end
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endmodule // template_body_1i1o
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sd_output #(8+2) sdout
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(
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// Outputs
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.ic_drdy (ic_drdy),
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.p_srdy (p_srdy),
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.p_data ({p_code,p_data}),
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// Inputs
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.clk (clk),
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.reset (reset),
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.ic_srdy (ic_srdy),
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.ic_data ({ic_code,ic_data}),
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.p_drdy (p_drdy));
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endmodule // template_1i1o
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// Local Variables:
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// Local Variables:
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// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
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// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
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// End:
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// End:
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