module egr_oflow
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module egr_oflow
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#(parameter drop_thr=`TX_FIFO_DEPTH-10)
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#(parameter drop_thr=`TX_FIFO_DEPTH-128)
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(
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(
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input clk,
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input clk,
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input reset,
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input reset,
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input c_srdy,
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input c_srdy,
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output reg c_drdy,
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output reg c_drdy,
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input [`PFW_SZ-1:0] c_data,
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input [`PFW_SZ-1:0] c_data,
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input [`TX_USG_SZ-1:0] tx_usage,
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input [`TX_USG_SZ-1:0] tx_usage,
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output reg p_srdy,
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output reg p_srdy,
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input p_drdy,
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input p_drdy,
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output [`PFW_SZ-1:0] p_data,
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output [`PFW_SZ-1:0] p_data,
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output reg p_commit,
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output reg p_commit,
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output reg p_abort
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output reg p_abort
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);
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);
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reg state, nxt_state;
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reg state, nxt_state;
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localparam s_idle = 0, s_packet = 1, s_flush = 2;
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localparam s_idle = 0, s_packet = 1, s_flush = 2;
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assign p_data = c_data;
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assign p_data = c_data;
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always @*
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always @*
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begin
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begin
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c_drdy = 0;
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c_drdy = 0;
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p_srdy = 0;
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p_srdy = 0;
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p_commit = 0;
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p_commit = 0;
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p_abort = 0;
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p_abort = 0;
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case (state)
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case (state)
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s_idle :
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s_idle :
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begin
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begin
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if (c_srdy & p_drdy & (c_data[`PRW_PCC] == `PCC_SOP))
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if (c_srdy & p_drdy & (c_data[`PRW_PCC] == `PCC_SOP))
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begin
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begin
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nxt_state = s_packet;
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nxt_state = s_packet;
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c_drdy = 1;
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c_drdy = 1;
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p_srdy = 1;
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p_srdy = 1;
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end
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end
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else if (c_srdy)
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else if (c_srdy)
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begin
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begin
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c_drdy = 1;
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c_drdy = 1;
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end
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end
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end // case: state[s_idle]
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end // case: state[s_idle]
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s_packet :
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s_packet :
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begin
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begin
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if (c_srdy & (c_data[`PRW_PCC] == `PCC_BADEOP))
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if (c_srdy & (c_data[`PRW_PCC] == `PCC_BADEOP))
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begin
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begin
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c_drdy = 1;
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c_drdy = 1;
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p_abort = 1;
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p_abort = 1;
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nxt_state = s_idle;
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nxt_state = s_idle;
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end
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end
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else if (c_srdy & p_drdy & (c_data[`PRW_PCC] == `PCC_EOP))
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else if (c_srdy & p_drdy & (c_data[`PRW_PCC] == `PCC_EOP))
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begin
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begin
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p_srdy = 1;
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p_srdy = 1;
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c_drdy = 1;
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c_drdy = 1;
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p_commit = 1;
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p_commit = 1;
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nxt_state = s_idle;
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nxt_state = s_idle;
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end
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end
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else if (tx_usage >= drop_thr)
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else if (!p_drdy | (tx_usage >= drop_thr))
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begin
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begin
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c_drdy = 1;
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c_drdy = 1;
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nxt_state = s_idle;
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nxt_state = s_idle;
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p_abort = 1;
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p_abort = 1;
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end
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end
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else if (c_srdy & p_drdy)
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else if (c_srdy & p_drdy)
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begin
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begin
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p_srdy = 1;
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p_srdy = 1;
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c_drdy = 1;
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c_drdy = 1;
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end
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end
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end // case: state[s_packet]
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end // case: state[s_packet]
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default : nxt_state = s_idle;
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default : nxt_state = s_idle;
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endcase // case (1'b1)
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endcase // case (1'b1)
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end // always @ *
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end // always @ *
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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state <= #1 s_idle;
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state <= #1 s_idle;
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end
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end
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else
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else
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begin
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begin
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state <= #1 nxt_state;
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state <= #1 nxt_state;
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end
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end
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end // always @ (posedge clk)
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end // always @ (posedge clk)
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endmodule // egr_oflow
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endmodule // egr_oflow
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