// packet parser
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// packet parser
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//
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//
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// Takes input packet on rxg interface and copies packet to pdo
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// Takes input packet on rxg interface and copies packet to pdo
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// interface, without changing packet data. If packet is too
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// interface, without changing packet data. If packet is too
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// short to be parsed, converts packet to an error code.
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// short to be parsed, converts packet to an error code.
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//
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//
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// If packet parses correctly and is not an error packet, sends
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// If packet parses correctly and is not an error packet, sends
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// a parse result to the FIB for lookup. Otherwise aborts the
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// a parse result to the FIB for lookup. Otherwise aborts the
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// packet so it is flushed from the packet FIFO.
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// packet so it is flushed from the packet FIFO.
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module pkt_parse
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module pkt_parse
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#(parameter port_num=0)
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(input clk,
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(input clk,
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input reset,
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input reset,
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input rxg_srdy,
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input rxg_srdy,
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output rxg_drdy,
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output rxg_drdy,
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input [1:0] rxg_code,
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input [1:0] rxg_code,
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input [7:0] rxg_data,
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input [7:0] rxg_data,
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output reg p2f_srdy,
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output reg p2f_srdy,
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input p2f_drdy,
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input p2f_drdy,
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output reg [`PAR_DATA_SZ-1:0] p2f_data,
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output reg [`PAR_DATA_SZ-1:0] p2f_data,
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output pdo_srdy,
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output pdo_srdy,
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input pdo_drdy,
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input pdo_drdy,
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output [1:0] pdo_code,
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output [1:0] pdo_code,
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output [7:0] pdo_data
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output [7:0] pdo_data
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);
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);
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wire lp_srdy;
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wire lp_srdy;
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reg lp_drdy;
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reg lp_drdy;
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wire [1:0] lp_code;
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wire [1:0] lp_code;
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wire [7:0] lp_data;
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wire [7:0] lp_data;
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reg lc_srdy;
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reg lc_srdy;
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wire lc_drdy;
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wire lc_drdy;
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reg [1:0] lc_code;
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reg [1:0] lc_code;
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reg [3:0] count, nxt_count;
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reg [3:0] count, nxt_count;
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reg nxt_p2f_srdy;
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reg nxt_p2f_srdy;
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reg [`PAR_DATA_SZ-1:0] nxt_p2f_data;
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reg [`PAR_DATA_SZ-1:0] nxt_p2f_data;
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sd_input #(8+2) rxg_in
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sd_input #(8+2) rxg_in
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(
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(
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// Outputs
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// Outputs
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.c_drdy (rxg_drdy),
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.c_drdy (rxg_drdy),
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.ip_srdy (lp_srdy),
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.ip_srdy (lp_srdy),
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.ip_data ({lp_code,lp_data}),
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.ip_data ({lp_code,lp_data}),
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.c_srdy (rxg_srdy),
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.c_srdy (rxg_srdy),
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.c_data ({rxg_code,rxg_data}),
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.c_data ({rxg_code,rxg_data}),
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.ip_drdy (lp_drdy));
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.ip_drdy (lp_drdy));
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always @*
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always @*
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begin
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begin
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nxt_p2f_srdy = p2f_srdy;
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nxt_p2f_srdy = p2f_srdy;
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nxt_p2f_data = p2f_data;
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nxt_p2f_data = p2f_data;
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nxt_count = count;
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nxt_count = count;
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lc_code = lp_code;
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lc_code = lp_code;
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if (p2f_srdy)
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if (p2f_srdy)
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begin
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begin
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lp_drdy = 0;
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lp_drdy = 0;
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lc_srdy = 0;
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lc_srdy = 0;
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if (p2f_drdy)
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if (p2f_drdy)
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nxt_p2f_srdy = 0;
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nxt_p2f_srdy = 0;
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end
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end
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else if (lp_srdy & lc_drdy)
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else if (lp_srdy & lc_drdy)
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begin
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begin
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lp_drdy = 1;
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lp_drdy = 1;
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lc_srdy = 1;
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lc_srdy = 1;
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case (count)
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case (count)
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0, 1, 2, 3, 4, 5 :
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0, 1, 2, 3, 4, 5 :
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begin
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begin
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if (count == 0)
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if (count == 0)
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begin
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nxt_p2f_data = 0;
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nxt_p2f_data = 0;
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nxt_p2f_data[`PAR_SRCPORT] = port_num;
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end
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if ((lp_code == `PCC_EOP) || (lp_code == `PCC_BADEOP))
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if ((lp_code == `PCC_EOP) || (lp_code == `PCC_BADEOP))
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begin
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begin
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lc_code = `PCC_BADEOP;
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lc_code = `PCC_BADEOP;
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nxt_count = 0;
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nxt_count = 0;
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end
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end
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else
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else
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begin
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begin
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nxt_p2f_data[`PAR_MACDA] = { p2f_data[`PAR_MACDA] << 8, lp_data };
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nxt_p2f_data[`PAR_MACDA] = { p2f_data[`PAR_MACDA] << 8, lp_data };
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nxt_count = count + 1;
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nxt_count = count + 1;
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end
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end
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end // case: 0, 1, 2, 3, 4, 5
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end // case: 0, 1, 2, 3, 4, 5
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6, 7, 8, 9, 10, 11 :
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6, 7, 8, 9, 10, 11 :
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begin
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begin
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if ((lp_code == `PCC_EOP) || (lp_code == `PCC_BADEOP))
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if ((lp_code == `PCC_EOP) || (lp_code == `PCC_BADEOP))
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begin
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begin
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lc_code = `PCC_BADEOP;
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lc_code = `PCC_BADEOP;
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nxt_count = 0;
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nxt_count = 0;
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end
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end
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else
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else
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begin
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begin
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nxt_p2f_data[`PAR_MACSA] = { p2f_data[`PAR_MACSA] << 8, lp_data };
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nxt_p2f_data[`PAR_MACSA] = { p2f_data[`PAR_MACSA] << 8, lp_data };
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nxt_count = count + 1;
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nxt_count = count + 1;
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end
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end
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end // case: 6, 7, 8, 9, 10, 11
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end // case: 6, 7, 8, 9, 10, 11
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// done with parsing, wait for packet EOP
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// done with parsing, wait for packet EOP
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12 :
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12 :
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begin
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begin
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if (lp_code == `PCC_EOP)
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if (lp_code == `PCC_EOP)
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begin
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begin
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nxt_p2f_srdy = 1;
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nxt_p2f_srdy = 1;
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nxt_count = 0;
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nxt_count = 0;
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end
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end
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else if (lp_code == `PCC_BADEOP)
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else if (lp_code == `PCC_BADEOP)
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nxt_count = 0;
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nxt_count = 0;
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end
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end
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default : nxt_count = 0;
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default : nxt_count = 0;
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endcase // case (count)
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endcase // case (count)
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end
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end
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else
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else
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begin
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begin
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lp_drdy = 0;
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lp_drdy = 0;
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lc_srdy = 0;
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lc_srdy = 0;
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end // else: !if(lp_srdy & lc_drdy)
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end // else: !if(lp_srdy & lc_drdy)
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end // always @ *
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end // always @ *
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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/*AUTORESET*/
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/*AUTORESET*/
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// Beginning of autoreset for uninitialized flops
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// Beginning of autoreset for uninitialized flops
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count <= 4'h0;
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count <= 4'h0;
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p2f_data <= {(1+(`PAR_DATA_SZ-1)){1'b0}};
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p2f_data <= {(1+(`PAR_DATA_SZ-1)){1'b0}};
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p2f_srdy <= 1'h0;
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p2f_srdy <= 1'h0;
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// End of automatics
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// End of automatics
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end
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end
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else
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else
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begin
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begin
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p2f_srdy <= #1 nxt_p2f_srdy;
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p2f_srdy <= #1 nxt_p2f_srdy;
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p2f_data <= #1 nxt_p2f_data;
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p2f_data <= #1 nxt_p2f_data;
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count <= #1 nxt_count;
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count <= #1 nxt_count;
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end
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end
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end
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end
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sd_output #(8+2) par_out
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sd_output #(8+2) par_out
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(
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(
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// Outputs
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// Outputs
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.ic_drdy (lc_drdy),
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.ic_drdy (lc_drdy),
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.p_srdy (pdo_srdy),
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.p_srdy (pdo_srdy),
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.p_data ({pdo_code,pdo_data}),
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.p_data ({pdo_code,pdo_data}),
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.ic_srdy (lc_srdy),
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.ic_srdy (lc_srdy),
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.ic_data ({lp_code,lp_data}),
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.ic_data ({lp_code,lp_data}),
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.p_drdy (pdo_drdy));
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.p_drdy (pdo_drdy));
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endmodule // pkt_parse
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endmodule // pkt_parse
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// Local Variables:
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// Local Variables:
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// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
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// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
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// End:
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// End:
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