module port_macro
|
module port_macro
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#(parameter port_num = 0)
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#(parameter port_num = 0)
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(input clk,
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(input clk,
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input reset,
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input reset,
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|
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input [`PRW_SZ-1:0] ri_data, // To ring_tap of port_ring_tap.v
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input [`PRW_SZ-1:0] ri_data, // To ring_tap of port_ring_tap.v
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output [`PRW_SZ-1:0] ro_data, // From ring_tap of port_ring_tap.v
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output [`PRW_SZ-1:0] ro_data, // From ring_tap of port_ring_tap.v
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input [`NUM_PORTS-1:0] fli_data, // To ring_tap of port_ring_tap.v
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input [`NUM_PORTS-1:0] fli_data, // To ring_tap of port_ring_tap.v
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/*AUTOINPUT*/
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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// Beginning of automatic inputs (from unused autoinst inputs)
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input fli_srdy, // To ring_tap of port_ring_tap.v
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input fli_srdy, // To ring_tap of port_ring_tap.v
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input gmii_rx_clk, // To port_clocking of port_clocking.v, ...
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input gmii_rx_clk, // To port_clocking of port_clocking.v, ...
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input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v
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input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v
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input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v
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input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v
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input p2f_drdy, // To pkt_parse of pkt_parse.v
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input p2f_drdy, // To pkt_parse of pkt_parse.v
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input rarb_ack, // To ring_tap of port_ring_tap.v
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input rarb_ack, // To ring_tap of port_ring_tap.v
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input ri_srdy, // To ring_tap of port_ring_tap.v
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input ri_srdy, // To ring_tap of port_ring_tap.v
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input ro_drdy, // To ring_tap of port_ring_tap.v
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input ro_drdy, // To ring_tap of port_ring_tap.v
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// End of automatics
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// End of automatics
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|
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output rarb_req,
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output rarb_req,
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output fli_drdy, // From ring_tap of port_ring_tap.v
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output fli_drdy, // From ring_tap of port_ring_tap.v
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output gmii_tx_en, // From tx_gmii of sd_tx_gigmac.v
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output gmii_tx_en, // From tx_gmii of sd_tx_gigmac.v
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output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v
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output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v
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output [`PAR_DATA_SZ-1:0] p2f_data, // From pkt_parse of pkt_parse.v
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output [`PAR_DATA_SZ-1:0] p2f_data, // From pkt_parse of pkt_parse.v
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output p2f_srdy, // From pkt_parse of pkt_parse.v
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output p2f_srdy, // From pkt_parse of pkt_parse.v
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output ri_drdy, // From ring_tap of port_ring_tap.v
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output ri_drdy, // From ring_tap of port_ring_tap.v
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output ro_srdy // From ring_tap of port_ring_tap.v
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output ro_srdy // From ring_tap of port_ring_tap.v
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);
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);
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|
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wire [`RX_USG_SZ-1:0] rx_usage;
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wire [`RX_USG_SZ-1:0] rx_usage;
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wire [`TX_USG_SZ-1:0] tx_usage;
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wire [`TX_USG_SZ-1:0] tx_usage;
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wire [`PFW_SZ-1:0] prx_data; // From fifo_rx of sd_fifo_b.v
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wire [`PFW_SZ-1:0] prx_data; // From fifo_rx of sd_fifo_b.v
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wire [`PFW_SZ-1:0] ptx_data; // From fifo_tx of sd_fifo_b.v
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wire [`PFW_SZ-1:0] ptx_data; // From fifo_tx of sd_fifo_b.v
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wire [`PFW_SZ-1:0] rttx_data; // From ring_tap of port_ring_tap.v
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wire [`PFW_SZ-1:0] rttx_data; // From ring_tap of port_ring_tap.v
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wire [1:0] rxg_code; // From rx_sync_fifo of sd_fifo_s.v
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wire [1:0] rxg_code; // From rx_sync_fifo of sd_fifo_s.v
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wire [7:0] rxg_data; // From rx_sync_fifo of sd_fifo_s.v
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wire [7:0] rxg_data; // From rx_sync_fifo of sd_fifo_s.v
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wire [`PFW_SZ-1:0] ctx_data; // From oflow of egr_oflow.v
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wire [`PFW_SZ-1:0] ctx_data; // From oflow of egr_oflow.v
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire crx_abort; // From con of concentrator.v
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wire crx_abort; // From con of concentrator.v
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wire crx_commit; // From con of concentrator.v
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wire crx_commit; // From con of concentrator.v
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wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v
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wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v
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wire crx_drdy; // From fifo_rx of sd_fifo_b.v
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wire crx_drdy; // From fifo_rx of sd_fifo_b.v
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wire crx_srdy; // From con of concentrator.v
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wire crx_srdy; // From con of concentrator.v
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wire ctx_abort; // From oflow of egr_oflow.v
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wire ctx_abort; // From oflow of egr_oflow.v
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wire ctx_commit; // From oflow of egr_oflow.v
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wire ctx_commit; // From oflow of egr_oflow.v
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wire ctx_drdy; // From fifo_tx of sd_fifo_b.v
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wire ctx_drdy; // From fifo_tx of sd_fifo_b.v
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wire ctx_srdy; // From oflow of egr_oflow.v
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wire ctx_srdy; // From oflow of egr_oflow.v
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wire gmii_rx_reset; // From port_clocking of port_clocking.v
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wire gmii_rx_reset; // From port_clocking of port_clocking.v
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wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v
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wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v
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wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v
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wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v
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wire pdo_drdy; // From con of concentrator.v
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wire pdo_drdy; // From con of concentrator.v
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wire pdo_srdy; // From pkt_parse of pkt_parse.v
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wire pdo_srdy; // From pkt_parse of pkt_parse.v
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wire prx_drdy; // From ring_tap of port_ring_tap.v
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wire prx_drdy; // From ring_tap of port_ring_tap.v
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wire prx_srdy; // From fifo_rx of sd_fifo_b.v
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wire prx_srdy; // From fifo_rx of sd_fifo_b.v
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wire ptx_drdy; // From dst of distributor.v
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wire ptx_drdy; // From dst of distributor.v
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wire ptx_srdy; // From fifo_tx of sd_fifo_b.v
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wire ptx_srdy; // From fifo_tx of sd_fifo_b.v
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wire rarb_req; // From ring_tap of port_ring_tap.v
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wire rttx_drdy; // From oflow of egr_oflow.v
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wire rttx_drdy; // From oflow of egr_oflow.v
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wire rttx_srdy; // From ring_tap of port_ring_tap.v
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wire rttx_srdy; // From ring_tap of port_ring_tap.v
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wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v
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wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v
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wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v
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wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v
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wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v
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wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v
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wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v
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wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v
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wire rxg_drdy; // From pkt_parse of pkt_parse.v
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wire rxg_drdy; // From pkt_parse of pkt_parse.v
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wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v
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wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v
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wire [1:0] txg_code; // From dst of distributor.v
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wire [1:0] txg_code; // From dst of distributor.v
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wire [7:0] txg_data; // From dst of distributor.v
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wire [7:0] txg_data; // From dst of distributor.v
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wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v
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wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v
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wire txg_srdy; // From dst of distributor.v
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wire txg_srdy; // From dst of distributor.v
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// End of automatics
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// End of automatics
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|
|
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port_clocking port_clocking
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port_clocking port_clocking
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.gmii_rx_reset (gmii_rx_reset),
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.gmii_rx_reset (gmii_rx_reset),
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.gmii_rx_clk (gmii_rx_clk));
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.gmii_rx_clk (gmii_rx_clk));
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|
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/* sd_rx_gigmac AUTO_TEMPLATE
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/* sd_rx_gigmac AUTO_TEMPLATE
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(
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(
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.clk (gmii_rx_clk),
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.clk (gmii_rx_clk),
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.reset (gmii_rx_reset),
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.reset (gmii_rx_reset),
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.rxg_\(.*\) (rxc_rxg_\1[]),
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.rxg_\(.*\) (rxc_rxg_\1[]),
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);
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);
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*/
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*/
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sd_rx_gigmac rx_gigmac
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sd_rx_gigmac rx_gigmac
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.rxg_srdy (rxc_rxg_srdy), // Templated
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.rxg_srdy (rxc_rxg_srdy), // Templated
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.rxg_code (rxc_rxg_code[1:0]), // Templated
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.rxg_code (rxc_rxg_code[1:0]), // Templated
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.rxg_data (rxc_rxg_data[7:0]), // Templated
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.rxg_data (rxc_rxg_data[7:0]), // Templated
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// Inputs
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// Inputs
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.clk (gmii_rx_clk), // Templated
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.clk (gmii_rx_clk), // Templated
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.reset (gmii_rx_reset), // Templated
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.reset (gmii_rx_reset), // Templated
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.gmii_rx_dv (gmii_rx_dv),
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.gmii_rx_dv (gmii_rx_dv),
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.gmii_rxd (gmii_rxd[7:0]),
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.gmii_rxd (gmii_rxd[7:0]),
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.rxg_drdy (rxc_rxg_drdy)); // Templated
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.rxg_drdy (rxc_rxg_drdy)); // Templated
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|
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/* sd_fifo_s AUTO_TEMPLATE
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/* sd_fifo_s AUTO_TEMPLATE
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(
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(
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.c_clk (gmii_rx_clk),
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.c_clk (gmii_rx_clk),
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.c_reset (gmii_rx_reset),
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.c_reset (gmii_rx_reset),
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.c_data ({rxc_rxg_code,rxc_rxg_data}),
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.c_data ({rxc_rxg_code,rxc_rxg_data}),
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.p_data ({rxg_code,rxg_data}),
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.p_data ({rxg_code,rxg_data}),
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.p_clk (clk),
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.p_clk (clk),
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.p_reset (reset),
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.p_reset (reset),
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.c_\(.*\) (rxc_rxg_\1[]),
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.c_\(.*\) (rxc_rxg_\1[]),
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.p_\(.*\) (rxg_\1[]),
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.p_\(.*\) (rxg_\1[]),
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);
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);
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*/
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*/
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sd_fifo_s #(8+2,16,1) rx_sync_fifo
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sd_fifo_s #(8+2,16,1) rx_sync_fifo
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.c_drdy (rxc_rxg_drdy), // Templated
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.c_drdy (rxc_rxg_drdy), // Templated
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.p_srdy (rxg_srdy), // Templated
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.p_srdy (rxg_srdy), // Templated
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.p_data ({rxg_code,rxg_data}), // Templated
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.p_data ({rxg_code,rxg_data}), // Templated
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// Inputs
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// Inputs
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.c_clk (gmii_rx_clk), // Templated
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.c_clk (gmii_rx_clk), // Templated
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.c_reset (gmii_rx_reset), // Templated
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.c_reset (gmii_rx_reset), // Templated
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.c_srdy (rxc_rxg_srdy), // Templated
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.c_srdy (rxc_rxg_srdy), // Templated
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.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated
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.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated
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.p_clk (clk), // Templated
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.p_clk (clk), // Templated
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.p_reset (reset), // Templated
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.p_reset (reset), // Templated
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.p_drdy (rxg_drdy)); // Templated
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.p_drdy (rxg_drdy)); // Templated
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|
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pkt_parse #(port_num) pkt_parse
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pkt_parse #(port_num) pkt_parse
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.rxg_drdy (rxg_drdy),
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.rxg_drdy (rxg_drdy),
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.p2f_srdy (p2f_srdy),
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.p2f_srdy (p2f_srdy),
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.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]),
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.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]),
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.pdo_srdy (pdo_srdy),
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.pdo_srdy (pdo_srdy),
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.pdo_code (pdo_code[1:0]),
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.pdo_code (pdo_code[1:0]),
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.pdo_data (pdo_data[7:0]),
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.pdo_data (pdo_data[7:0]),
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.rxg_srdy (rxg_srdy),
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.rxg_srdy (rxg_srdy),
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.rxg_code (rxg_code[1:0]),
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.rxg_code (rxg_code[1:0]),
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.rxg_data (rxg_data[7:0]),
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.rxg_data (rxg_data[7:0]),
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.p2f_drdy (p2f_drdy),
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.p2f_drdy (p2f_drdy),
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.pdo_drdy (pdo_drdy));
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.pdo_drdy (pdo_drdy));
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|
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/* concentrator AUTO_TEMPLATE
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/* concentrator AUTO_TEMPLATE
|
(
|
(
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.c_\(.*\) (pdo_\1[]),
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.c_\(.*\) (pdo_\1[]),
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.p_\(.*\) (crx_\1[]),
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.p_\(.*\) (crx_\1[]),
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);
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);
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*/
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*/
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concentrator con
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concentrator con
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.c_drdy (pdo_drdy), // Templated
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.c_drdy (pdo_drdy), // Templated
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.p_data (crx_data[`PFW_SZ-1:0]), // Templated
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.p_data (crx_data[`PFW_SZ-1:0]), // Templated
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.p_srdy (crx_srdy), // Templated
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.p_srdy (crx_srdy), // Templated
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.p_commit (crx_commit), // Templated
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.p_commit (crx_commit), // Templated
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.p_abort (crx_abort), // Templated
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.p_abort (crx_abort), // Templated
|
// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.c_data (pdo_data[7:0]), // Templated
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.c_data (pdo_data[7:0]), // Templated
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.c_code (pdo_code[1:0]), // Templated
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.c_code (pdo_code[1:0]), // Templated
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.c_srdy (pdo_srdy), // Templated
|
.c_srdy (pdo_srdy), // Templated
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.p_drdy (crx_drdy)); // Templated
|
.p_drdy (crx_drdy)); // Templated
|
|
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/* sd_fifo_b AUTO_TEMPLATE "fifo_\(.*\)"
|
/* sd_fifo_b AUTO_TEMPLATE "fifo_\(.*\)"
|
(
|
(
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.p_abort (1'b0),
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.p_abort (1'b0),
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.p_commit (1'b0),
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.p_commit (1'b0),
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.usage (@_usage),
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.c_usage (@_usage),
|
|
.p_usage (),
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.c_\(.*\) (c@_\1),
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.c_\(.*\) (c@_\1),
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.p_\(.*\) (p@_\1),
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.p_\(.*\) (p@_\1),
|
);
|
);
|
*/
|
*/
|
sd_fifo_b #(`PFW_SZ, `RX_FIFO_DEPTH, 0, 1) fifo_rx
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sd_fifo_b #(`PFW_SZ, `RX_FIFO_DEPTH, 0, 1) fifo_rx
|
(/*AUTOINST*/
|
(/*AUTOINST*/
|
// Outputs
|
// Outputs
|
.c_drdy (crx_drdy), // Templated
|
.c_drdy (crx_drdy), // Templated
|
.p_srdy (prx_srdy), // Templated
|
.p_srdy (prx_srdy), // Templated
|
.p_data (prx_data), // Templated
|
.p_data (prx_data), // Templated
|
.usage (rx_usage), // Templated
|
.p_usage (), // Templated
|
|
.c_usage (rx_usage), // Templated
|
// Inputs
|
// Inputs
|
.clk (clk),
|
.clk (clk),
|
.reset (reset),
|
.reset (reset),
|
.c_srdy (crx_srdy), // Templated
|
.c_srdy (crx_srdy), // Templated
|
.c_commit (crx_commit), // Templated
|
.c_commit (crx_commit), // Templated
|
.c_abort (crx_abort), // Templated
|
.c_abort (crx_abort), // Templated
|
.c_data (crx_data), // Templated
|
.c_data (crx_data), // Templated
|
.p_drdy (prx_drdy), // Templated
|
.p_drdy (prx_drdy), // Templated
|
.p_commit (1'b0), // Templated
|
.p_commit (1'b0), // Templated
|
.p_abort (1'b0)); // Templated
|
.p_abort (1'b0)); // Templated
|
|
|
sd_fifo_b #(`PFW_SZ, `TX_FIFO_DEPTH, 0, 1) fifo_tx
|
sd_fifo_b #(`PFW_SZ, `TX_FIFO_DEPTH, 0, 1) fifo_tx
|
(/*AUTOINST*/
|
(/*AUTOINST*/
|
// Outputs
|
// Outputs
|
.c_drdy (ctx_drdy), // Templated
|
.c_drdy (ctx_drdy), // Templated
|
.p_srdy (ptx_srdy), // Templated
|
.p_srdy (ptx_srdy), // Templated
|
.p_data (ptx_data), // Templated
|
.p_data (ptx_data), // Templated
|
.usage (tx_usage), // Templated
|
.p_usage (), // Templated
|
|
.c_usage (tx_usage), // Templated
|
// Inputs
|
// Inputs
|
.clk (clk),
|
.clk (clk),
|
.reset (reset),
|
.reset (reset),
|
.c_srdy (ctx_srdy), // Templated
|
.c_srdy (ctx_srdy), // Templated
|
.c_commit (ctx_commit), // Templated
|
.c_commit (ctx_commit), // Templated
|
.c_abort (ctx_abort), // Templated
|
.c_abort (ctx_abort), // Templated
|
.c_data (ctx_data), // Templated
|
.c_data (ctx_data), // Templated
|
.p_drdy (ptx_drdy), // Templated
|
.p_drdy (ptx_drdy), // Templated
|
.p_commit (1'b0), // Templated
|
.p_commit (1'b0), // Templated
|
.p_abort (1'b0)); // Templated
|
.p_abort (1'b0)); // Templated
|
|
|
/* port_ring_tap AUTO_TEMPLATE
|
/* port_ring_tap AUTO_TEMPLATE
|
(
|
(
|
.ro_data (ro_data[`PRW_SZ-1:0]),
|
.ro_data (ro_data[`PRW_SZ-1:0]),
|
.ri_data (ri_data[`PRW_SZ-1:0]),
|
.ri_data (ri_data[`PRW_SZ-1:0]),
|
.prx_\(.*\) (prx_\1),
|
.prx_\(.*\) (prx_\1),
|
.ptx_\(.*\) (rttx_\1),
|
.ptx_\(.*\) (rttx_\1),
|
);
|
);
|
*/
|
*/
|
port_ring_tap #(port_num) ring_tap
|
port_ring_tap #(port_num) ring_tap
|
(/*AUTOINST*/
|
(/*AUTOINST*/
|
// Outputs
|
// Outputs
|
.ri_drdy (ri_drdy),
|
.ri_drdy (ri_drdy),
|
.prx_drdy (prx_drdy), // Templated
|
.prx_drdy (prx_drdy), // Templated
|
.ro_srdy (ro_srdy),
|
.ro_srdy (ro_srdy),
|
.ro_data (ro_data[`PRW_SZ-1:0]), // Templated
|
.ro_data (ro_data[`PRW_SZ-1:0]), // Templated
|
.ptx_srdy (rttx_srdy), // Templated
|
.ptx_srdy (rttx_srdy), // Templated
|
.ptx_data (rttx_data), // Templated
|
.ptx_data (rttx_data), // Templated
|
.fli_drdy (fli_drdy),
|
.fli_drdy (fli_drdy),
|
.rarb_req (rarb_req),
|
.rarb_req (rarb_req),
|
// Inputs
|
// Inputs
|
.clk (clk),
|
.clk (clk),
|
.reset (reset),
|
.reset (reset),
|
.ri_srdy (ri_srdy),
|
.ri_srdy (ri_srdy),
|
.ri_data (ri_data[`PRW_SZ-1:0]), // Templated
|
.ri_data (ri_data[`PRW_SZ-1:0]), // Templated
|
.prx_srdy (prx_srdy), // Templated
|
.prx_srdy (prx_srdy), // Templated
|
.prx_data (prx_data), // Templated
|
.prx_data (prx_data), // Templated
|
.ro_drdy (ro_drdy),
|
.ro_drdy (ro_drdy),
|
.ptx_drdy (rttx_drdy), // Templated
|
.ptx_drdy (rttx_drdy), // Templated
|
.fli_srdy (fli_srdy),
|
.fli_srdy (fli_srdy),
|
.fli_data (fli_data[`NUM_PORTS-1:0]),
|
.fli_data (fli_data[`NUM_PORTS-1:0]),
|
.rarb_ack (rarb_ack));
|
.rarb_ack (rarb_ack));
|
|
|
/* egr_oflow AUTO_TEMPLATE
|
/* egr_oflow AUTO_TEMPLATE
|
(
|
(
|
.c_\(.*\) (rttx_\1[]),
|
.c_\(.*\) (rttx_\1[]),
|
.p_\(.*\) (ctx_\1[]),
|
.p_\(.*\) (ctx_\1[]),
|
);
|
);
|
*/
|
*/
|
egr_oflow oflow
|
egr_oflow oflow
|
(/*AUTOINST*/
|
(/*AUTOINST*/
|
// Outputs
|
// Outputs
|
.c_drdy (rttx_drdy), // Templated
|
.c_drdy (rttx_drdy), // Templated
|
.p_srdy (ctx_srdy), // Templated
|
.p_srdy (ctx_srdy), // Templated
|
.p_data (ctx_data[`PFW_SZ-1:0]), // Templated
|
.p_data (ctx_data[`PFW_SZ-1:0]), // Templated
|
.p_commit (ctx_commit), // Templated
|
.p_commit (ctx_commit), // Templated
|
.p_abort (ctx_abort), // Templated
|
.p_abort (ctx_abort), // Templated
|
// Inputs
|
// Inputs
|
.clk (clk),
|
.clk (clk),
|
.reset (reset),
|
.reset (reset),
|
.c_srdy (rttx_srdy), // Templated
|
.c_srdy (rttx_srdy), // Templated
|
.c_data (rttx_data[`PFW_SZ-1:0]), // Templated
|
.c_data (rttx_data[`PFW_SZ-1:0]), // Templated
|
.tx_usage (tx_usage[`TX_USG_SZ-1:0]),
|
.tx_usage (tx_usage[`TX_USG_SZ-1:0]),
|
.p_drdy (ctx_drdy)); // Templated
|
.p_drdy (ctx_drdy)); // Templated
|
|
|
/* distributor AUTO_TEMPLATE
|
/* distributor AUTO_TEMPLATE
|
(
|
(
|
.p_\(.*\) (txg_\1[]),
|
.p_\(.*\) (txg_\1[]),
|
);
|
);
|
*/
|
*/
|
distributor dst
|
distributor dst
|
(/*AUTOINST*/
|
(/*AUTOINST*/
|
// Outputs
|
// Outputs
|
.ptx_drdy (ptx_drdy),
|
.ptx_drdy (ptx_drdy),
|
.p_srdy (txg_srdy), // Templated
|
.p_srdy (txg_srdy), // Templated
|
.p_code (txg_code[1:0]), // Templated
|
.p_code (txg_code[1:0]), // Templated
|
.p_data (txg_data[7:0]), // Templated
|
.p_data (txg_data[7:0]), // Templated
|
// Inputs
|
// Inputs
|
.clk (clk),
|
.clk (clk),
|
.reset (reset),
|
.reset (reset),
|
.ptx_srdy (ptx_srdy),
|
.ptx_srdy (ptx_srdy),
|
.ptx_data (ptx_data[`PFW_SZ-1:0]),
|
.ptx_data (ptx_data[`PFW_SZ-1:0]),
|
.p_drdy (txg_drdy)); // Templated
|
.p_drdy (txg_drdy)); // Templated
|
|
|
sd_tx_gigmac tx_gmii
|
sd_tx_gigmac tx_gmii
|
(/*AUTOINST*/
|
(/*AUTOINST*/
|
// Outputs
|
// Outputs
|
.gmii_tx_en (gmii_tx_en),
|
.gmii_tx_en (gmii_tx_en),
|
.gmii_txd (gmii_txd[7:0]),
|
.gmii_txd (gmii_txd[7:0]),
|
.txg_drdy (txg_drdy),
|
.txg_drdy (txg_drdy),
|
// Inputs
|
// Inputs
|
.clk (clk),
|
.clk (clk),
|
.reset (reset),
|
.reset (reset),
|
.txg_srdy (txg_srdy),
|
.txg_srdy (txg_srdy),
|
.txg_code (txg_code[1:0]),
|
.txg_code (txg_code[1:0]),
|
.txg_data (txg_data[7:0]));
|
.txg_data (txg_data[7:0]));
|
|
|
endmodule // port_macro
|
endmodule // port_macro
|
// Local Variables:
|
// Local Variables:
|
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks")
|
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks")
|
// End:
|
// End:
|
|
|
