// Inputs are ri (Ring In), ro (Ring Out),
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// Inputs are ri (Ring In), ro (Ring Out),
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// fli (FIB lookup in), prx (port in/RX), and ptx (port out/TX)
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// fli (FIB lookup in), prx (port in/RX), and ptx (port out/TX)
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module port_ring_tap
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module port_ring_tap
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#(parameter portnum = 0,
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#(parameter portnum = 0,
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parameter rdp_sz = `PRW_SZ,
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parameter rdp_sz = `PRW_SZ,
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parameter pdp_sz = `PFW_SZ
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parameter pdp_sz = `PFW_SZ
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)
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)
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(
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(
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input clk,
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input clk,
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input reset,
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input reset,
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input ri_srdy,
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input ri_srdy,
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output ri_drdy,
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output ri_drdy,
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input [rdp_sz-1:0] ri_data,
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input [rdp_sz-1:0] ri_data,
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input prx_srdy,
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input prx_srdy,
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output prx_drdy,
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output prx_drdy,
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input [pdp_sz-1:0] prx_data,
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input [pdp_sz-1:0] prx_data,
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output ro_srdy,
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output ro_srdy,
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input ro_drdy,
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input ro_drdy,
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output [rdp_sz-1:0] ro_data,
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output [rdp_sz-1:0] ro_data,
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output ptx_srdy,
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output ptx_srdy,
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input ptx_drdy,
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input ptx_drdy,
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output [pdp_sz-1:0] ptx_data,
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output [pdp_sz-1:0] ptx_data,
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input fli_srdy,
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input fli_srdy,
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output fli_drdy,
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output fli_drdy,
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input [`NUM_PORTS-1:0] fli_data
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input [`NUM_PORTS-1:0] fli_data,
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output rarb_req,
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input rarb_ack
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);
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);
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wire [`PRW_SZ-1:0] lri_data; // From tc_ri of sd_input.v
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wire [`PRW_SZ-1:0] lri_data; // From tc_ri of sd_input.v
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wire [`NUM_PORTS-1:0] lfli_data; // From tc_fli of sd_input.v
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wire [`NUM_PORTS-1:0] lfli_data; // From tc_fli of sd_input.v
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wire [`PFW_SZ-1:0] lprx_data; // From tc_prx of sd_input.v
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wire [`PFW_SZ-1:0] lprx_data; // From tc_prx of sd_input.v
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wire [`PFW_SZ-1:0] lptx_data; // From fsm of port_ring_tap_fsm.v
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wire [`PFW_SZ-1:0] lptx_data; // From fsm of port_ring_tap_fsm.v
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wire [`PRW_SZ-1:0] lro_data; // From fsm of port_ring_tap_fsm.v
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wire [`PRW_SZ-1:0] lro_data; // From fsm of port_ring_tap_fsm.v
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/*AUTOWIRE*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire lfli_drdy; // From fsm of port_ring_tap_fsm.v
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wire lfli_drdy; // From fsm of port_ring_tap_fsm.v
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wire lfli_srdy; // From tc_fli of sd_input.v
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wire lfli_srdy; // From tc_fli of sd_input.v
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wire lprx_drdy; // From fsm of port_ring_tap_fsm.v
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wire lprx_drdy; // From fsm of port_ring_tap_fsm.v
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wire lprx_srdy; // From tc_prx of sd_input.v
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wire lprx_srdy; // From tc_prx of sd_input.v
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wire lptx_drdy; // From tc_ptx of sd_output.v
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wire lptx_drdy; // From tc_ptx of sd_output.v
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wire lptx_srdy; // From fsm of port_ring_tap_fsm.v
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wire lptx_srdy; // From fsm of port_ring_tap_fsm.v
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wire lri_drdy; // From fsm of port_ring_tap_fsm.v
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wire lri_drdy; // From fsm of port_ring_tap_fsm.v
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wire lri_srdy; // From tc_ri of sd_input.v
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wire lri_srdy; // From tc_ri of sd_input.v
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wire lro_drdy; // From tc_ro of sd_output.v
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wire lro_drdy; // From tc_ro of sd_output.v
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wire lro_srdy; // From fsm of port_ring_tap_fsm.v
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wire lro_srdy; // From fsm of port_ring_tap_fsm.v
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// End of automatics
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// End of automatics
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/* sd_input AUTO_TEMPLATE "tc_\(.*\)"
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/* sd_input AUTO_TEMPLATE "tc_\(.*\)"
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(
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(
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.c_\(.*\) (@_\1),
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.c_\(.*\) (@_\1),
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.ip_\(.*\) (l@_\1),
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.ip_\(.*\) (l@_\1),
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);
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);
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*/
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*/
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sd_input #(rdp_sz) tc_ri
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sd_input #(rdp_sz) tc_ri
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.c_drdy (ri_drdy), // Templated
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.c_drdy (ri_drdy), // Templated
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.ip_srdy (lri_srdy), // Templated
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.ip_srdy (lri_srdy), // Templated
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.ip_data (lri_data), // Templated
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.ip_data (lri_data), // Templated
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.c_srdy (ri_srdy), // Templated
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.c_srdy (ri_srdy), // Templated
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.c_data (ri_data), // Templated
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.c_data (ri_data), // Templated
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.ip_drdy (lri_drdy)); // Templated
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.ip_drdy (lri_drdy)); // Templated
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sd_input #(pdp_sz) tc_prx
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sd_input #(pdp_sz) tc_prx
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.c_drdy (prx_drdy), // Templated
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.c_drdy (prx_drdy), // Templated
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.ip_srdy (lprx_srdy), // Templated
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.ip_srdy (lprx_srdy), // Templated
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.ip_data (lprx_data), // Templated
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.ip_data (lprx_data), // Templated
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.c_srdy (prx_srdy), // Templated
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.c_srdy (prx_srdy), // Templated
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.c_data (prx_data), // Templated
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.c_data (prx_data), // Templated
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.ip_drdy (lprx_drdy)); // Templated
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.ip_drdy (lprx_drdy)); // Templated
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sd_input #(`NUM_PORTS) tc_fli
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sd_input #(`NUM_PORTS) tc_fli
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.c_drdy (fli_drdy), // Templated
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.c_drdy (fli_drdy), // Templated
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.ip_srdy (lfli_srdy), // Templated
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.ip_srdy (lfli_srdy), // Templated
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.ip_data (lfli_data), // Templated
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.ip_data (lfli_data), // Templated
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.c_srdy (fli_srdy), // Templated
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.c_srdy (fli_srdy), // Templated
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.c_data (fli_data), // Templated
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.c_data (fli_data), // Templated
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.ip_drdy (lfli_drdy)); // Templated
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.ip_drdy (lfli_drdy)); // Templated
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port_ring_tap_fsm #(rdp_sz, pdp_sz, portnum) fsm
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port_ring_tap_fsm #(rdp_sz, pdp_sz, portnum) fsm
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.lfli_drdy (lfli_drdy),
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.lfli_drdy (lfli_drdy),
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.lprx_drdy (lprx_drdy),
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.lprx_drdy (lprx_drdy),
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.lptx_data (lptx_data[pdp_sz-1:0]),
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.lptx_data (lptx_data[pdp_sz-1:0]),
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.lptx_srdy (lptx_srdy),
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.lptx_srdy (lptx_srdy),
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.lri_drdy (lri_drdy),
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.lri_drdy (lri_drdy),
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.lro_data (lro_data[rdp_sz-1:0]),
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.lro_data (lro_data[rdp_sz-1:0]),
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.lro_srdy (lro_srdy),
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.lro_srdy (lro_srdy),
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.rarb_req (rarb_req),
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.lfli_data (lfli_data[`NUM_PORTS-1:0]),
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.lfli_data (lfli_data[`NUM_PORTS-1:0]),
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.lfli_srdy (lfli_srdy),
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.lfli_srdy (lfli_srdy),
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.lprx_data (lprx_data[pdp_sz-1:0]),
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.lprx_data (lprx_data[pdp_sz-1:0]),
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.lprx_srdy (lprx_srdy),
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.lprx_srdy (lprx_srdy),
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.lptx_drdy (lptx_drdy),
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.lptx_drdy (lptx_drdy),
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.lri_data (lri_data[rdp_sz-1:0]),
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.lri_data (lri_data[rdp_sz-1:0]),
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.lri_srdy (lri_srdy),
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.lri_srdy (lri_srdy),
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.lro_drdy (lro_drdy));
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.lro_drdy (lro_drdy),
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.rarb_ack (rarb_ack));
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/* sd_output AUTO_TEMPLATE "tc_\(.*\)"
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/* sd_output AUTO_TEMPLATE "tc_\(.*\)"
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(
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(
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.ic_\(.*\) (l@_\1),
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.ic_\(.*\) (l@_\1),
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.p_\(.*\) (@_\1),
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.p_\(.*\) (@_\1),
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);
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);
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*/
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*/
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sd_output #(pdp_sz) tc_ptx
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sd_output #(pdp_sz) tc_ptx
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.ic_drdy (lptx_drdy), // Templated
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.ic_drdy (lptx_drdy), // Templated
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.p_srdy (ptx_srdy), // Templated
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.p_srdy (ptx_srdy), // Templated
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.p_data (ptx_data), // Templated
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.p_data (ptx_data), // Templated
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.ic_srdy (lptx_srdy), // Templated
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.ic_srdy (lptx_srdy), // Templated
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.ic_data (lptx_data), // Templated
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.ic_data (lptx_data), // Templated
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.p_drdy (ptx_drdy)); // Templated
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.p_drdy (ptx_drdy)); // Templated
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sd_output #(rdp_sz) tc_ro
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sd_output #(rdp_sz) tc_ro
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(/*AUTOINST*/
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(/*AUTOINST*/
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// Outputs
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// Outputs
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.ic_drdy (lro_drdy), // Templated
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.ic_drdy (lro_drdy), // Templated
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.p_srdy (ro_srdy), // Templated
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.p_srdy (ro_srdy), // Templated
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.p_data (ro_data), // Templated
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.p_data (ro_data), // Templated
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// Inputs
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// Inputs
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.clk (clk),
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.clk (clk),
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.reset (reset),
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.reset (reset),
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.ic_srdy (lro_srdy), // Templated
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.ic_srdy (lro_srdy), // Templated
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.ic_data (lro_data), // Templated
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.ic_data (lro_data), // Templated
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.p_drdy (ro_drdy)); // Templated
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.p_drdy (ro_drdy)); // Templated
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endmodule // port_ring_tap
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endmodule // port_ring_tap
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// Local Variables:
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// Local Variables:
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// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
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// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
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// End:
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// End:
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