//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Srdy/Drdy FIFO Head "B"
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// Srdy/Drdy FIFO Head "B"
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//
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//
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// Building block for FIFOs. The "B" (big) FIFO is design for larger FIFOs
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// Building block for FIFOs. The "B" (big) FIFO is design for larger FIFOs
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// based around memories, with sizes that may not be a power of 2. This
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// based around memories, with sizes that may not be a power of 2. This
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// FIFO has a limitation that at most (depth-1) entries may be used.
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// FIFO has a limitation that at most (depth-1) entries may be used.
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//
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//
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// The bound inputs allow multiple FIFO controllers to share a single
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// The bound inputs allow multiple FIFO controllers to share a single
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// memory. The enable input is for arbitration between multiple FIFO
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// memory. The enable input is for arbitration between multiple FIFO
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// controllers, or between the fifo head and tail controllers on a
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// controllers, or between the fifo head and tail controllers on a
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// single port memory.
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// single port memory.
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//
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//
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// The commit parameter enables write/commit behavior. This creates
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// The commit parameter enables write/commit behavior. This creates
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// two write pointers, one which is used for writing to memory and
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// two write pointers, one which is used for writing to memory and
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// a commit pointer which is sent to the tail block.
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// a commit pointer which is sent to the tail block.
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//
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//
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// Naming convention: c = consumer, p = producer, i = internal interface
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// Naming convention: c = consumer, p = producer, i = internal interface
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Author: Guy Hutchison
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// Author: Guy Hutchison
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//
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//
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// This block is uncopyrighted and released into the public domain.
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// This block is uncopyrighted and released into the public domain.
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// delay unit for nonblocking assigns, default is to #1
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// delay unit for nonblocking assigns, default is to #1
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`ifndef SDLIB_DELAY
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`ifndef SDLIB_DELAY
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`define SDLIB_DELAY #1
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`define SDLIB_DELAY #1
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`endif
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`endif
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module sd_fifo_head_b
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module sd_fifo_head_b
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#(parameter depth=16,
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#(parameter depth=16,
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parameter commit=0,
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parameter commit=0,
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parameter asz=$clog2(depth)
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parameter asz=$clog2(depth),
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parameter usz=$clog2(depth+1)
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)
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)
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(
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(
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input clk,
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input clk,
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input reset,
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input reset,
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input enable,
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input enable,
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input c_commit,
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input c_commit,
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input c_abort, // should be asserted when c_srdy == 0
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input c_abort, // should be asserted when c_srdy == 0
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input c_srdy,
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input c_srdy,
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output c_drdy,
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output c_drdy,
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input [asz-1:0] bound_low,
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input [asz-1:0] bound_low,
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input [asz-1:0] bound_high,
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input [asz-1:0] bound_high,
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|
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input [asz-1:0] rdptr,
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input [asz-1:0] rdptr,
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output reg [asz-1:0] cur_wrptr,
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output reg [asz-1:0] cur_wrptr,
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output reg [asz-1:0] com_wrptr,
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output reg [asz-1:0] com_wrptr,
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output reg [usz-1:0] c_usage,
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output reg mem_we
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output reg mem_we
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);
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);
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reg [asz-1:0] nxt_wrptr;
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reg [asz-1:0] nxt_wrptr;
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reg [asz-1:0] wrptr_p1;
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reg [asz-1:0] wrptr_p1;
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reg empty;
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reg empty;
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reg full, nxt_full;
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reg full, nxt_full;
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reg [asz-1:0] nxt_com_wrptr;
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reg [asz-1:0] nxt_com_wrptr;
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reg [usz:0] tmp_usage;
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wire [usz-1:0] fifo_size;
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assign fifo_size = bound_high - bound_low + 1;
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assign c_drdy = !nxt_full & enable;
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assign c_drdy = !nxt_full & enable;
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always @*
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always @*
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begin
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begin
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if (cur_wrptr[asz-1:0] == bound_high)
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if (cur_wrptr[asz-1:0] == bound_high)
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begin
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begin
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wrptr_p1[asz-1:0] = bound_low;
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wrptr_p1[asz-1:0] = bound_low;
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end
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end
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else
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else
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wrptr_p1 = cur_wrptr + 1;
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wrptr_p1 = cur_wrptr + 1;
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//empty = (cur_wrptr == rdptr) & !full;
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//empty = (cur_wrptr == rdptr) & !full;
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empty = (cur_wrptr == rdptr);
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empty = (cur_wrptr == rdptr);
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|
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// special-case -- if we do abort on a full FIFO
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// special-case -- if we do abort on a full FIFO
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// force full flag to clear
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// force full flag to clear
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/* -----\/----- EXCLUDED -----\/-----
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/* -----\/----- EXCLUDED -----\/-----
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if ((commit == 1) && c_abort && full)
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if ((commit == 1) && c_abort && full)
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nxt_full = 0;
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nxt_full = 0;
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else
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else
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nxt_full = ( (!full & (wrptr_p1 == rdptr)) | (full & (cur_wrptr == rdptr)));
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nxt_full = ( (!full & (wrptr_p1 == rdptr)) | (full & (cur_wrptr == rdptr)));
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-----/\----- EXCLUDED -----/\----- */
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-----/\----- EXCLUDED -----/\----- */
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nxt_full = (wrptr_p1 == rdptr);
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nxt_full = (wrptr_p1 == rdptr);
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if ((commit == 1) && c_abort)
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if ((commit == 1) && c_abort)
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begin
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begin
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nxt_wrptr = com_wrptr;
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nxt_wrptr = com_wrptr;
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end
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end
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else if (enable & c_srdy & !nxt_full)
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else if (enable & c_srdy & !nxt_full)
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begin
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begin
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nxt_wrptr = wrptr_p1;
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nxt_wrptr = wrptr_p1;
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mem_we = 1;
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mem_we = 1;
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end
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end
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else
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else
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begin
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begin
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nxt_wrptr = cur_wrptr;
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nxt_wrptr = cur_wrptr;
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mem_we = 0;
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mem_we = 0;
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end
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end
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tmp_usage = cur_wrptr[asz-1:0] - rdptr[asz-1:0];
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if (~tmp_usage[usz])
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c_usage = tmp_usage[usz-1:0];
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else
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c_usage = fifo_size - (rdptr[asz-1:0] - cur_wrptr[asz-1:0]);
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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cur_wrptr <= `SDLIB_DELAY bound_low;
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cur_wrptr <= `SDLIB_DELAY bound_low;
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full <= `SDLIB_DELAY 0;
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full <= `SDLIB_DELAY 0;
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end
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end
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else
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else
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begin
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begin
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cur_wrptr <= `SDLIB_DELAY nxt_wrptr;
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cur_wrptr <= `SDLIB_DELAY nxt_wrptr;
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full <= `SDLIB_DELAY nxt_full;
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full <= `SDLIB_DELAY nxt_full;
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end // else: !if(reset)
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end // else: !if(reset)
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end // always @ (posedge clk)
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end // always @ (posedge clk)
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generate
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generate
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if (commit)
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if (commit)
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begin
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begin
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always @*
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always @*
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begin
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begin
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if (enable & c_commit & !c_abort & c_srdy & !nxt_full)
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if (enable & c_commit & !c_abort & c_srdy & !nxt_full)
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nxt_com_wrptr = wrptr_p1;
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nxt_com_wrptr = wrptr_p1;
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else
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else
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nxt_com_wrptr = com_wrptr;
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nxt_com_wrptr = com_wrptr;
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (reset)
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if (reset)
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com_wrptr <= `SDLIB_DELAY bound_low;
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com_wrptr <= `SDLIB_DELAY bound_low;
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else
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else
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com_wrptr <= `SDLIB_DELAY nxt_com_wrptr;
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com_wrptr <= `SDLIB_DELAY nxt_com_wrptr;
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end
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end
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end // if (commit)
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end // if (commit)
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else
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else
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begin
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begin
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always @*
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always @*
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com_wrptr = cur_wrptr;
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com_wrptr = cur_wrptr;
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end
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end
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endgenerate
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endgenerate
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endmodule // fifo_head
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endmodule // fifo_head
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