//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Srdy/Drdy FIFO Tail "B"
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// Srdy/Drdy FIFO Tail "B"
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//
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//
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// Building block for FIFOs. The "B" (big) FIFO is design for larger FIFOs
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// Building block for FIFOs. The "B" (big) FIFO is design for larger FIFOs
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// based around memories, with sizes that may not be a power of 2.
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// based around memories, with sizes that may not be a power of 2.
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//
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//
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// The bound inputs allow multiple FIFO controllers to share a single
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// The bound inputs allow multiple FIFO controllers to share a single
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// memory. The enable input is for arbitration between multiple FIFO
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// memory. The enable input is for arbitration between multiple FIFO
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// controllers, or between the fifo head and tail controllers on a
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// controllers, or between the fifo head and tail controllers on a
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// single port memory.
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// single port memory.
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//
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//
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// The commit parameter enables read/commit behavior. This creates
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// The commit parameter enables read/commit behavior. This creates
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// two read pointers, one which is used for reading from memory and
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// two read pointers, one which is used for reading from memory and
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// a commit pointer which is sent to the head block. The abort behavior
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// a commit pointer which is sent to the head block. The abort behavior
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// has a 3-cycle performance penalty due to pipeline flush.
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// has a 3-cycle performance penalty due to pipeline flush.
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//
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//
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// The FIFO tail assumes a memory with one-cycle read latency, and
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// The FIFO tail assumes a memory with one-cycle read latency, and
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// has output buffering to compensate for this.
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// has output buffering to compensate for this.
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//
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//
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// Naming convention: c = consumer, p = producer, i = internal interface
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// Naming convention: c = consumer, p = producer, i = internal interface
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Author: Guy Hutchison
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// Author: Guy Hutchison
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//
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//
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// This block is uncopyrighted and released into the public domain.
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// This block is uncopyrighted and released into the public domain.
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Clocking statement for synchronous blocks. Default is for
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// Clocking statement for synchronous blocks. Default is for
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// posedge clocking and positive async reset
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// posedge clocking and positive async reset
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`ifndef SDLIB_CLOCKING
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`ifndef SDLIB_CLOCKING
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`define SDLIB_CLOCKING posedge clk or posedge reset
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`define SDLIB_CLOCKING posedge clk or posedge reset
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`endif
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`endif
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// delay unit for nonblocking assigns, default is to #1
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// delay unit for nonblocking assigns, default is to #1
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`ifndef SDLIB_DELAY
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`ifndef SDLIB_DELAY
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`define SDLIB_DELAY #1
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`define SDLIB_DELAY #1
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`endif
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`endif
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module sd_fifo_tail_b
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module sd_fifo_tail_b
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#(parameter width=8,
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#(parameter width=8,
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parameter depth=16,
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parameter depth=16,
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parameter commit=0,
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parameter commit=0,
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parameter asz=$clog2(depth),
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parameter asz=$clog2(depth),
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parameter usz=$clog2(depth+1)
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parameter usz=$clog2(depth+1)
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)
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)
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(
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(
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input clk,
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input clk,
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input reset,
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input reset,
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input enable,
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input enable,
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input [asz-1:0] bound_low,
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input [asz-1:0] bound_low,
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input [asz-1:0] bound_high,
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input [asz-1:0] bound_high,
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|
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output reg [asz-1:0] cur_rdptr,
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output reg [asz-1:0] cur_rdptr,
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output reg [asz-1:0] com_rdptr,
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output reg [asz-1:0] com_rdptr,
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input [asz-1:0] wrptr,
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input [asz-1:0] wrptr,
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output reg mem_re,
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output reg mem_re,
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input mem_we,
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input mem_we,
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output reg [usz-1:0] p_usage,
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output reg [usz-1:0] p_usage,
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|
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output p_srdy,
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output p_srdy,
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input p_drdy,
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input p_drdy,
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input p_commit,
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input p_commit,
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input p_abort,
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input p_abort,
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input [width-1:0] mem_rd_data,
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input [width-1:0] mem_rd_data,
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output [width-1:0] p_data
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output [width-1:0] p_data
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);
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);
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reg [asz-1:0] nxt_cur_rdptr;
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reg [asz-1:0] nxt_cur_rdptr;
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reg [asz-1:0] cur_rdptr_p1;
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reg [asz-1:0] cur_rdptr_p1;
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reg empty, full;
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reg empty, full;
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|
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reg nxt_irdy;
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reg nxt_irdy;
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reg [width-1:0] hold_a, hold_b;
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reg [width-1:0] hold_a, hold_b;
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reg valid_a, valid_b;
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reg valid_a, valid_b;
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reg prev_re;
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reg prev_re;
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reg [usz:0] tmp_usage;
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reg [usz:0] tmp_usage;
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reg [usz:0] fifo_size;
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reg [usz:0] fifo_size;
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wire rbuf1_drdy;
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wire rbuf1_drdy;
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wire ip_srdy, ip_drdy;
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wire ip_srdy, ip_drdy;
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wire [width-1:0] ip_data;
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wire [width-1:0] ip_data;
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// Stage 1 -- Read pipeline
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// Stage 1 -- Read pipeline
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// issue a read if:
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// issue a read if:
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// 1) we are enabled
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// 1) we are enabled
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// 2) valid_a is 0, OR
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// 2) valid_a is 0, OR
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// 3) valid_b is 0, OR
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// 3) valid_b is 0, OR
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// 4) valid_a && valid_b && trdy
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// 4) valid_a && valid_b && trdy
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always @*
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always @*
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begin
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begin
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|
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if (cur_rdptr[asz-1:0] == (bound_high))
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if (cur_rdptr[asz-1:0] == (bound_high))
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begin
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begin
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cur_rdptr_p1[asz-1:0] = bound_low;
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cur_rdptr_p1[asz-1:0] = bound_low;
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end
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end
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else
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else
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cur_rdptr_p1 = cur_rdptr + 1;
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cur_rdptr_p1 = cur_rdptr + 1;
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|
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empty = (wrptr == cur_rdptr);
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empty = (wrptr == cur_rdptr);
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|
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if (commit && p_abort)
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if (commit && p_abort)
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begin
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begin
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nxt_cur_rdptr = com_rdptr;
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nxt_cur_rdptr = com_rdptr;
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mem_re = 0;
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mem_re = 0;
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end
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end
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else if (enable & !empty & ip_drdy)
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else if (enable & !empty & (ip_drdy | (rbuf1_drdy & !prev_re)))
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begin
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begin
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nxt_cur_rdptr = cur_rdptr_p1;
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nxt_cur_rdptr = cur_rdptr_p1;
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mem_re = 1;
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mem_re = 1;
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end
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end
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else
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else
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begin
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begin
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nxt_cur_rdptr = cur_rdptr;
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nxt_cur_rdptr = cur_rdptr;
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mem_re = 0;
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mem_re = 0;
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end // else: !if(enable & !empty & (!valid_a | !valid_b |...
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end // else: !if(enable & !empty & (!valid_a | !valid_b |...
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fifo_size = (bound_high - bound_low + 1);
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fifo_size = (bound_high - bound_low + 1);
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tmp_usage = wrptr[asz-1:0] - cur_rdptr[asz-1:0];
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tmp_usage = wrptr[asz-1:0] - cur_rdptr[asz-1:0];
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if (~tmp_usage[usz])
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if (~tmp_usage[usz])
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p_usage = tmp_usage[usz-1:0];
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p_usage = tmp_usage[usz-1:0];
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else
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else
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p_usage = fifo_size - (cur_rdptr[asz-1:0] - wrptr[asz-1:0]);
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p_usage = fifo_size - (cur_rdptr[asz-1:0] - wrptr[asz-1:0]);
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end // always @ *
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end // always @ *
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (reset)
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if (reset)
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cur_rdptr <= `SDLIB_DELAY bound_low;
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cur_rdptr <= `SDLIB_DELAY bound_low;
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else
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else
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cur_rdptr <= `SDLIB_DELAY nxt_cur_rdptr;
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cur_rdptr <= `SDLIB_DELAY nxt_cur_rdptr;
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end
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end
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reg [asz-1:0] rdaddr_s0, rdaddr_a, rdaddr_b;
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reg [asz-1:0] rdaddr_s0, rdaddr_a, rdaddr_b;
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reg [asz-1:0] nxt_com_rdptr;
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reg [asz-1:0] nxt_com_rdptr;
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generate
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generate
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if (commit == 1)
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if (commit == 1)
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begin : gen_s0
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begin : gen_s0
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (reset)
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if (reset)
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com_rdptr <= `SDLIB_DELAY bound_low;
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com_rdptr <= `SDLIB_DELAY bound_low;
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else
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else
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com_rdptr <= `SDLIB_DELAY nxt_com_rdptr;
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com_rdptr <= `SDLIB_DELAY nxt_com_rdptr;
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if (mem_re)
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if (mem_re)
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rdaddr_s0 <= `SDLIB_DELAY cur_rdptr;
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rdaddr_s0 <= `SDLIB_DELAY cur_rdptr;
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end
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end
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end
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end
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else
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else
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begin : gen_ns0
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begin : gen_ns0
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always @*
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always @*
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com_rdptr = cur_rdptr;
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com_rdptr = cur_rdptr;
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end
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end
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endgenerate
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endgenerate
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// Stage 2 -- read buffering
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// Stage 2 -- read buffering
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always @(`SDLIB_CLOCKING)
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always @(`SDLIB_CLOCKING)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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prev_re <= `SDLIB_DELAY 0;
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prev_re <= `SDLIB_DELAY 0;
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end
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end
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else
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else
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begin
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begin
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if (commit && p_abort)
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if (commit && p_abort)
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prev_re <= `SDLIB_DELAY 0;
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prev_re <= `SDLIB_DELAY 0;
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else
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else
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prev_re <= `SDLIB_DELAY mem_re;
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prev_re <= `SDLIB_DELAY mem_re;
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end // else: !if(reset)
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end // else: !if(reset)
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end // always @ (`SDLIB_CLOCKING)
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end // always @ (`SDLIB_CLOCKING)
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generate
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generate
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if (commit == 1)
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if (commit == 1)
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begin : gen_s2
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begin : gen_s2
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wire [asz-1:0] ip_rdaddr, p_rdaddr;
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wire [asz-1:0] ip_rdaddr, p_rdaddr;
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sd_input #(asz+width) rbuf1
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sd_input #(asz+width) rbuf1
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(.clk (clk), .reset (p_abort | reset),
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(.clk (clk), .reset (p_abort | reset),
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.c_srdy (prev_re),
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.c_srdy (prev_re),
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.c_drdy (rbuf1_drdy),
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.c_drdy (rbuf1_drdy),
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.c_data ({rdaddr_s0,mem_rd_data}),
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.c_data ({rdaddr_s0,mem_rd_data}),
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.ip_srdy (ip_srdy), .ip_drdy (ip_drdy),
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.ip_srdy (ip_srdy), .ip_drdy (ip_drdy),
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.ip_data ({ip_rdaddr,ip_data}));
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.ip_data ({ip_rdaddr,ip_data}));
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sd_output #(asz+width) rbuf2
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sd_output #(asz+width) rbuf2
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(.clk (clk), .reset (p_abort | reset),
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(.clk (clk), .reset (p_abort | reset),
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.ic_srdy (ip_srdy),
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.ic_srdy (ip_srdy),
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.ic_drdy (ip_drdy),
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.ic_drdy (ip_drdy),
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.ic_data ({ip_rdaddr,ip_data}),
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.ic_data ({ip_rdaddr,ip_data}),
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.p_srdy (p_srdy), .p_drdy (p_drdy),
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.p_srdy (p_srdy), .p_drdy (p_drdy),
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.p_data ({p_rdaddr,p_data}));
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.p_data ({p_rdaddr,p_data}));
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always @*
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always @*
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begin
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begin
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if (p_commit & p_srdy & p_drdy)
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if (p_commit & p_srdy & p_drdy)
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nxt_com_rdptr = p_rdaddr;
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nxt_com_rdptr = p_rdaddr;
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else
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else
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nxt_com_rdptr = com_rdptr;
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nxt_com_rdptr = com_rdptr;
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end
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end
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end // if (commit == 1)
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end // if (commit == 1)
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else
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else
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begin : gen_ns2
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begin : gen_ns2
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sd_input #(width) rbuf1
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sd_input #(width) rbuf1
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(.clk (clk), .reset (p_abort | reset),
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(.clk (clk), .reset (p_abort | reset),
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.c_srdy (prev_re),
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.c_srdy (prev_re),
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.c_drdy (rbuf1_drdy),
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.c_drdy (rbuf1_drdy),
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.c_data (mem_rd_data),
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.c_data (mem_rd_data),
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.ip_srdy (ip_srdy), .ip_drdy (ip_drdy),
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.ip_srdy (ip_srdy), .ip_drdy (ip_drdy),
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.ip_data (ip_data));
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.ip_data (ip_data));
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|
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sd_output #(width) rbuf2
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sd_output #(width) rbuf2
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(.clk (clk), .reset (p_abort | reset),
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(.clk (clk), .reset (p_abort | reset),
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.ic_srdy (ip_srdy),
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.ic_srdy (ip_srdy),
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.ic_drdy (ip_drdy),
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.ic_drdy (ip_drdy),
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.ic_data (ip_data),
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.ic_data (ip_data),
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.p_srdy (p_srdy), .p_drdy (p_drdy),
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.p_srdy (p_srdy), .p_drdy (p_drdy),
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.p_data (p_data));
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.p_data (p_data));
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end // else: !if(commit == 1)
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end // else: !if(commit == 1)
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endgenerate
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endgenerate
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endmodule // it_fifo
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endmodule // it_fifo
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