//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Srdy/Drdy output block
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// Srdy/Drdy output block
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//
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//
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// Halts timing on all signals except ic_drdy
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// Halts timing on all signals except ic_drdy
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// ic_drdy is a combinatorial path from p_drdy
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// ic_drdy is a combinatorial path from p_drdy
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//
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//
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// Naming convention: c = consumer, p = producer, i = internal interface
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// Naming convention: c = consumer, p = producer, i = internal interface
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Author: Guy Hutchison
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// Author: Guy Hutchison
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//
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//
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// This block is uncopyrighted and released into the public domain.
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// This block is uncopyrighted and released into the public domain.
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Clocking statement for synchronous blocks. Default is for
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// Clocking statement for synchronous blocks. Default is for
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// posedge clocking and positive async reset
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// posedge clocking and positive async reset
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`ifndef SDLIB_CLOCKING
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`ifndef SDLIB_CLOCKING
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`define SDLIB_CLOCKING posedge clk or posedge reset
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`define SDLIB_CLOCKING posedge clk or posedge reset
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`endif
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`endif
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// delay unit for nonblocking assigns, default is to #1
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// delay unit for nonblocking assigns, default is to #1
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`ifndef SDLIB_DELAY
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`ifndef SDLIB_DELAY
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`define SDLIB_DELAY #1
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`define SDLIB_DELAY #1
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`endif
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`endif
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module sd_output
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module sd_output
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#(parameter width = 8)
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#(parameter width = 8)
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(
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(
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input clk,
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input clk,
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input reset,
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input reset,
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input ic_srdy,
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input ic_srdy,
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output reg ic_drdy,
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output reg ic_drdy,
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input [width-1:0] ic_data,
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input [width-1:0] ic_data,
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|
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output reg p_srdy,
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output reg p_srdy,
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input p_drdy,
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input p_drdy,
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output reg [width-1:0] p_data
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output reg [width-1:0] p_data
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);
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);
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reg load; // true when data will be loaded into p_data
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reg load; // true when data will be loaded into p_data
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reg drain; // true when data will be emptied from p_data
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reg hold; // true when data will be held in p_data
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reg nxt_p_srdy;
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reg nxt_p_srdy;
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|
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always @*
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always @*
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begin
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begin
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drain = p_srdy & p_drdy;
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ic_drdy = p_drdy | !p_srdy;
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hold = p_srdy & !p_drdy;
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ic_drdy = drain | !p_srdy;
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load = ic_srdy & ic_drdy;
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load = ic_srdy & ic_drdy;
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nxt_p_srdy = load | hold;
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nxt_p_srdy = load | (p_srdy & !p_drdy);
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end
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end
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always @(`SDLIB_CLOCKING)
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always @(`SDLIB_CLOCKING)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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p_srdy <= `SDLIB_DELAY 0;
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p_srdy <= `SDLIB_DELAY 0;
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end
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end
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else
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else
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begin
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begin
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p_srdy <= `SDLIB_DELAY nxt_p_srdy;
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p_srdy <= `SDLIB_DELAY nxt_p_srdy;
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end // else: !if(reset)
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end // else: !if(reset)
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end // always @ (posedge clk)
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end // always @ (posedge clk)
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always @(posedge clk)
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always @(posedge clk)
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if (load)
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if (load)
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p_data <= `SDLIB_DELAY ic_data;
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p_data <= `SDLIB_DELAY ic_data;
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|
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endmodule // it_output
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endmodule // it_output
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