//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Srdy/drdy assymetric join
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// Srdy/drdy assymetric join
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//
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//
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// Performs assymetric join of 2 inputs by concatination. Efficiency
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// Performs assymetric join of 2 inputs by concatination. Efficiency
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// of 0.5.
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// of 0.5.
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//
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//
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// Naming convention: c = consumer, p = producer, i = internal interface
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// Naming convention: c = consumer, p = producer, i = internal interface
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Author: Guy Hutchison
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// Author: Guy Hutchison
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//
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//
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// This block is uncopyrighted and released into the public domain.
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// This block is uncopyrighted and released into the public domain.
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Clocking statement for synchronous blocks. Default is for
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// Clocking statement for synchronous blocks. Default is for
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// posedge clocking and positive async reset
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// posedge clocking and positive async reset
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`ifndef SDLIB_CLOCKING
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`ifndef SDLIB_CLOCKING
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`define SDLIB_CLOCKING posedge clk or posedge reset
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`define SDLIB_CLOCKING posedge clk or posedge reset
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`endif
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`endif
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// delay unit for nonblocking assigns, default is to #1
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// delay unit for nonblocking assigns, default is to #1
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`ifndef SDLIB_DELAY
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`ifndef SDLIB_DELAY
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`define SDLIB_DELAY #1
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`define SDLIB_DELAY #1
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`endif
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`endif
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module sd_ajoin2
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module sd_ajoin2
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#(parameter c1_width=8,
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#(parameter c1_width=8,
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parameter c2_width=8)
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parameter c2_width=8)
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(
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(
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input clk;
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input clk,
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input reset,
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input reset,
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input c1_srdy,
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input c1_srdy,
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output c1_drdy,
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output c1_drdy,
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input [c1_width-1:0] c1_data,
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input [c1_width-1:0] c1_data,
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input c2_srdy,
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input c2_srdy,
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output c2_drdy,
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output c2_drdy,
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input [c2_width-1:0] c2_data,
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input [c2_width-1:0] c2_data,
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output p_srdy,
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output p_srdy,
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input p_drdy,
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input p_drdy,
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output reg [c1_width+c2_width-1:0] p_data
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output reg [c1_width+c2_width-1:0] p_data
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);
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);
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reg [c1_width+c2_width-1:0] nxt_p_data;
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reg [c1_width+c2_width-1:0] nxt_p_data;
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reg [1:0] in_drdy, nxt_in_drdy;
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reg [1:0] in_drdy, nxt_in_drdy;
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assign {c2_drdy,c1_drdy} = in_drdy;
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assign {c2_drdy,c1_drdy} = in_drdy;
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always @*
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always @*
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begin
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begin
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nxt_p_data = p_data;
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nxt_p_data = p_data;
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nxt_in_drdy = in_drdy;
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nxt_in_drdy = in_drdy;
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if (in_drdy[0])
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if (in_drdy[0])
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begin
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begin
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if (c1_srdy)
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if (c1_srdy)
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begin
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begin
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nxt_in_drdy[0] = 0;
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nxt_in_drdy[0] = 0;
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nxt_p_data[c1_width-1:0] = c1_data;
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nxt_p_data[c1_width-1:0] = c1_data;
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end
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end
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end
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end
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else if (p_srdy & p_drdy)
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else if (p_srdy & p_drdy)
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nxt_in_drdy[0] = 1;
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nxt_in_drdy[0] = 1;
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if (in_drdy[1])
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if (in_drdy[1])
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begin
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begin
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if (c2_srdy)
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if (c2_srdy)
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begin
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begin
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nxt_in_drdy[1] = 0;
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nxt_in_drdy[1] = 0;
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nxt_p_data[c2_width+c1_width-1:c1_width] = c2_data;
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nxt_p_data[c2_width+c1_width-1:c1_width] = c2_data;
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end
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end
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end
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end
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else if (p_srdy & p_drdy)
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else if (p_srdy & p_drdy)
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nxt_in_drdy[1] = 1;
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nxt_in_drdy[1] = 1;
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end
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end
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always @(`SDLIB_CLOCKING)
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always @(`SDLIB_CLOCKING)
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begin
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begin
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if (reset)
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if (reset)
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begin
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begin
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in_drdy <= `SDLIB_DELAY 2'b11;
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in_drdy <= `SDLIB_DELAY 2'b11;
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p_data <= `SDLIB_DELAY 0;
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p_data <= `SDLIB_DELAY 0;
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end
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end
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else
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else
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begin
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begin
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in_drdy <= `SDLIB_DELAY nxt_in_drdy;
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in_drdy <= `SDLIB_DELAY nxt_in_drdy;
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p_data <= `SDLIB_DELAY nxt_p_data;
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p_data <= `SDLIB_DELAY nxt_p_data;
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end // else: !if(reset)
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end // else: !if(reset)
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end // always @ (posedge clk)
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end // always @ (posedge clk)
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assign p_srdy = & (~in_drdy);
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assign p_srdy = & (~in_drdy);
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endmodule // it_output
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endmodule // it_output
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