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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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// Author: Guy Hutchison
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// Author: Guy Hutchison
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//
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//
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// This block is uncopyrighted and released into the public domain.
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// This block is uncopyrighted and released into the public domain.
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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module behave1p_mem
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module behave1p_mem
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#(parameter depth=256,
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#(parameter depth=256,
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parameter width=8,
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parameter width=8,
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parameter addr_sz=$clog2(depth))
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parameter addr_sz=$clog2(depth))
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(/*AUTOARG*/
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(/*AUTOARG*/
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// Outputs
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// Outputs
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d_out,
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d_out,
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// Inputs
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// Inputs
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wr_en, rd_en, clk, d_in, addr
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wr_en, rd_en, clk, d_in, addr
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);
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);
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input wr_en, rd_en, clk;
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input wr_en, rd_en, clk;
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input [width-1:0] d_in;
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input [width-1:0] d_in;
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input [addr_sz-1:0] addr;
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input [addr_sz-1:0] addr;
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output [width-1:0] d_out;
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output [width-1:0] d_out;
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reg [addr_sz-1:0] r_addr;
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reg [addr_sz-1:0] r_addr;
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reg [width-1:0] array[0:depth-1];
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reg [width-1:0] array[0:depth-1];
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always @(posedge clk)
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always @(posedge clk)
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begin
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begin
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if (wr_en)
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if (wr_en)
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begin
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begin
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array[addr] <= #1 d_in;
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array[addr] <= #1 d_in;
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end
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end
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else if (rd_en)
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else if (rd_en)
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begin
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begin
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r_addr <= #1 addr;
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r_addr <= #1 addr;
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end
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end
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end // always @ (posedge clk)
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end // always @ (posedge clk)
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assign d_out = array[r_addr];
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assign d_out = array[r_addr];
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`ifndef verilator
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genvar g;
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genvar g;
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generate
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generate
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for (g=0; g<depth; g=g+1)
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for (g=0; g<depth; g=g+1)
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begin : breakout
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begin : breakout
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wire [width-1:0] brk;
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wire [width-1:0] brk;
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assign brk=array[g];
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assign brk=array[g];
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end
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end
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endgenerate
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endgenerate
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`endif
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endmodule
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endmodule
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