----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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---- ----
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---- ----
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---- ----
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---- ----
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---- This file is part of the srl_fifo project ----
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---- This file is part of the srl_fifo project ----
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---- http://www.opencores.org/cores/srl_fifo ----
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---- http://www.opencores.org/cores/srl_fifo ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- Implementation of srl_fifo IP core according to ----
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---- Implementation of srl_fifo IP core according to ----
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---- srl_fifo IP core specification document. ----
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---- srl_fifo IP core specification document. ----
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---- ----
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---- ----
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---- To Do: ----
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---- To Do: ----
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---- NA ----
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---- NA ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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---- Andrew Mulcock, amulcock@opencores.org ----
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---- Andrew Mulcock, amulcock@opencores.org ----
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---- ----
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---- ----
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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---- ----
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---- ----
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---- Copyright (C) 2008 Authors and OPENCORES.ORG ----
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---- Copyright (C) 2008 Authors and OPENCORES.ORG ----
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---- ----
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---- ----
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---- This source file may be used and distributed without ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- later version. ----
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---- ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- details. ----
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---- ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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---- ----
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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-- ----
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-- ----
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-- CVS Revision History ----
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-- CVS Revision History ----
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-- ----
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-- ----
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-- $Log: not supported by cvs2svn $ ----
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-- $Log: not supported by cvs2svn $ ----
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-- ----
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-- ----
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--
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--
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-- quick description
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-- quick description
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--
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--
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-- Based upon the using a shift register as a fifo which has been
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-- Based upon the using a shift register as a fifo which has been
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-- around for years ( decades ), but really came of use to VHDL
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-- around for years ( decades ), but really came of use to VHDL
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-- when the Xilinx FPGA's started having SRL's.
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-- when the Xilinx FPGA's started having SRL's.
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--
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--
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-- In my view, the definitive article on shift register logic fifo's
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-- In my view, the definitive article on shift register logic fifo's
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-- comes from Mr Chapman at Xilinx, in the form of his BBFIFO
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-- comes from Mr Chapman at Xilinx, in the form of his BBFIFO
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-- tecXeclusive article, which as at early 2008, Xilinx have
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-- tecXeclusive article, which as at early 2008, Xilinx have
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-- removed.
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-- removed.
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--
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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ENTITY tb_srl_fifo_16_vhd IS
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ENTITY tb_srl_fifo_16_vhd IS
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END tb_srl_fifo_16_vhd;
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END tb_srl_fifo_16_vhd;
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ARCHITECTURE behavior OF tb_srl_fifo_16_vhd IS
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ARCHITECTURE behavior OF tb_srl_fifo_16_vhd IS
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constant width_tb : integer := 8;
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constant width_tb : integer := 8;
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT srl_fifo_16
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COMPONENT srl_fifo_16
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GENERIC ( width : integer := width_tb ); -- set to how wide fifo is to be
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GENERIC ( width : integer := width_tb ); -- set to how wide fifo is to be
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PORT(
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PORT(
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data_in : IN std_logic_vector(width_tb - 1 downto 0);
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data_in : IN std_logic_vector(width_tb - 1 downto 0);
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reset : IN std_logic;
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reset : IN std_logic;
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write : IN std_logic;
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write : IN std_logic;
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read : IN std_logic;
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read : IN std_logic;
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clk : IN std_logic;
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clk : IN std_logic;
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data_out : OUT std_logic_vector(width_tb - 1 downto 0);
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data_out : OUT std_logic_vector(width_tb - 1 downto 0);
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full : OUT std_logic;
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full : OUT std_logic;
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half_full : OUT std_logic;
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half_full : OUT std_logic;
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data_present : OUT std_logic
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data_present : OUT std_logic
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);
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);
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END COMPONENT;
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END COMPONENT;
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--Inputs
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--Inputs
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SIGNAL reset : std_logic := '0';
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SIGNAL reset : std_logic := '0';
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SIGNAL write : std_logic := '0';
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SIGNAL write : std_logic := '0';
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SIGNAL read : std_logic := '0';
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SIGNAL read : std_logic := '0';
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SIGNAL clk : std_logic := '0';
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SIGNAL clk : std_logic := '0';
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SIGNAL data_in : std_logic_vector(width_tb - 1 downto 0) := (others=>'0');
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SIGNAL data_in : std_logic_vector(width_tb - 1 downto 0) := (others=>'0');
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--Outputs
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--Outputs
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SIGNAL data_out : std_logic_vector(width_tb -1 downto 0);
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SIGNAL data_out : std_logic_vector(width_tb -1 downto 0);
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SIGNAL full : std_logic;
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SIGNAL full : std_logic;
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SIGNAL half_full : std_logic;
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SIGNAL half_full : std_logic;
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SIGNAL data_present : std_logic;
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SIGNAL data_present : std_logic;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: srl_fifo_16
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uut: srl_fifo_16
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GENERIC MAP (
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GENERIC MAP (
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width => width_tb
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width => width_tb
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)
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)
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PORT MAP(
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PORT MAP(
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data_in => data_in,
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data_in => data_in,
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data_out => data_out,
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data_out => data_out,
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reset => reset,
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reset => reset,
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write => write,
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write => write,
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read => read,
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read => read,
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full => full,
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full => full,
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half_full => half_full,
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half_full => half_full,
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data_present => data_present,
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data_present => data_present,
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clk => clk
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clk => clk
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);
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);
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tb : PROCESS
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tb : PROCESS
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BEGIN
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BEGIN
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reset <= '1';
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reset <= '1';
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-- Wait 100 ns for global reset to finish
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-- Wait 100 ns for global reset to finish
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wait for 100 ns;
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wait for 100 ns;
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wait until clk = '0';
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wait until clk = '0';
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reset <= '0';
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reset <= '0';
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-- Place stimulus here
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-- Place stimulus here
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wait until clk = '0'; -- 0
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wait until clk = '0'; -- 0
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data_in <= X"AA";
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data_in <= X"AA";
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write <= '1';
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write <= '1';
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wait until clk = '0'; -- 1
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wait until clk = '0'; -- 1
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data_in <= X"55";
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data_in <= X"55";
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wait until clk = '0'; -- 2
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wait until clk = '0'; -- 2
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data_in <= X"02";
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data_in <= X"02";
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wait until clk = '0'; -- 3
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wait until clk = '0'; -- 3
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data_in <= X"03";
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data_in <= X"03";
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wait until clk = '0'; -- 4
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wait until clk = '0'; -- 4
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data_in <= X"04";
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data_in <= X"04";
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wait until clk = '0'; -- 5
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wait until clk = '0'; -- 5
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data_in <= X"05";
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data_in <= X"05";
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wait until clk = '0'; -- 6
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wait until clk = '0'; -- 6
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data_in <= X"06";
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data_in <= X"06";
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wait until clk = '0'; -- 7
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wait until clk = '0'; -- 7
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data_in <= X"07";
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data_in <= X"07";
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wait until clk = '0'; -- 8
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wait until clk = '0'; -- 8
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data_in <= X"08";
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data_in <= X"08";
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wait until clk = '0'; -- 9
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wait until clk = '0'; -- 9
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data_in <= X"09";
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data_in <= X"09";
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wait until clk = '0'; -- A
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wait until clk = '0'; -- A
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data_in <= X"A0";
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data_in <= X"A0";
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wait until clk = '0'; -- B
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wait until clk = '0'; -- B
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data_in <= X"B0";
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data_in <= X"B0";
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wait until clk = '0'; -- C
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wait until clk = '0'; -- C
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data_in <= X"C0";
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data_in <= X"C0";
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wait until clk = '0'; -- D
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wait until clk = '0'; -- D
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data_in <= X"D0";
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data_in <= X"D0";
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wait until clk = '0'; -- E
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wait until clk = '0'; -- E
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data_in <= X"E0";
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data_in <= X"E0";
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wait until clk = '0'; -- F
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wait until clk = '0'; -- F
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data_in <= X"F0";
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data_in <= X"F0";
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wait until clk = '0'; -- no write
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wait until clk = '0'; -- no write
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data_in <= X"FF";
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data_in <= X"FF";
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wait until clk = '0'; -- write and read on full, reads first out
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wait until clk = '0'; -- write and read on full, reads first out
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data_in <= X"EE";
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data_in <= X"EE";
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read <= '1';
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read <= '1';
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wait until clk = '0'; -- no read or write
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wait until clk = '0'; -- no read or write
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data_in <= X"AB";
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data_in <= X"AB";
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read <= '0';
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read <= '0';
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write <= '0';
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write <= '0';
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-- read untill empty
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-- read untill empty
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wait until clk = '0';
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wait until clk = '0';
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read <= '1';
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read <= '1';
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for i in 0 to 13 loop -- read out 13 more
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for i in 0 to 13 loop -- read out 13 more
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wait until clk = '0';
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wait until clk = '0';
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end loop;
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end loop;
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read <= '0';
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read <= '0';
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wait until clk = '0'; -- dont read,
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wait until clk = '0'; -- dont read,
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read <= '1';
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read <= '1';
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wait until clk = '0'; -- read last - 1 out
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wait until clk = '0'; -- read last - 1 out
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read <= '0';
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read <= '0';
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wait until clk = '0'; -- dont read,
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wait until clk = '0'; -- dont read,
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read <= '1';
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read <= '1';
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wait until clk = '0'; -- read last out
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wait until clk = '0'; -- read last out
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read <= '0'; -- stop reading
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read <= '0'; -- stop reading
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wait; -- will wait forever
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wait; -- will wait forever
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END PROCESS;
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END PROCESS;
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-- clock gen process
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-- clock gen process
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process
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process
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begin
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begin
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wait for 1 ns;
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wait for 1 ns;
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clk <= '0';
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clk <= '0';
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wait for 1 ns;
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wait for 1 ns;
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clk <= '1';
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clk <= '1';
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end process;
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end process;
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END;
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END;
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