//
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//
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// PERIPHERAL UART_Rx: @NAME@
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// PERIPHERAL UART_Rx: @NAME@
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// Copyright 2013-2015 Sinclair R.F., Inc.
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//
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//
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// Technique:
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// Technique:
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// - optionally synchronize the incoming signal
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// - optionally synchronize the incoming signal
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// - optionally deglitch the incoming signal
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// - optionally deglitch the incoming signal
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// - identify edges, align with value before the edge
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// - identify edges, align with value before the edge
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// - generate missing edges, align values
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// - generate missing edges, align values
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// - assemble received bit sequence
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// - assemble received bit sequence
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// - run state machine counting number of received bits and waiting for delayed start bits
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// - run state machine counting number of received bits and waiting for delayed start bits
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// - validate bit sequence and output bit sequence at end of last stop bit
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// - validate bit sequence and output bit sequence at end of last stop bit
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// - optional FIFO
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// - optional FIFO
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//
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//
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localparam L__BAUDMETHOD = ((@BAUDMETHOD@)+1)/2;
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localparam L__BAUDMETHOD = ((@BAUDMETHOD@)+1)/2;
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localparam L__BAUDMETHOD_MINUS = L__BAUDMETHOD - 2;
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localparam L__BAUDMETHOD_MINUS = L__BAUDMETHOD - 2;
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localparam L__BAUDMETHOD_NBITS = $clog2(L__BAUDMETHOD+1);
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localparam L__BAUDMETHOD_NBITS = $clog2(L__BAUDMETHOD_MINUS+1);
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localparam L__SYNC_LENGTH = @SYNC@;
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localparam L__SYNC_LENGTH = @SYNC@;
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localparam L__DEGLITCH_LENGTH = @DEGLITCH@;
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localparam L__DEGLITCH_LENGTH = @DEGLITCH@;
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localparam L__NSTOP = @NSTOP@;
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localparam L__NSTOP = @NSTOP@;
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localparam L__NRX = 1+8+L__NSTOP;
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localparam L__NRX = 1+8+L__NSTOP;
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localparam L__EVENT_COUNT = 2*L__NRX-1;
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localparam L__EVENT_COUNT = 2*L__NRX-1;
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localparam L__EVENT_COUNT_NBITS = $clog2(L__EVENT_COUNT+1);
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localparam L__EVENT_COUNT_NBITS = $clog2(L__EVENT_COUNT+1);
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localparam L__INFIFO = @INFIFO@;
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localparam L__INFIFO = @INFIFO@;
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localparam L__INFIFO_NBITS = $clog2((L__INFIFO==0)?1:L__INFIFO);
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localparam L__INFIFO_NBITS = $clog2((L__INFIFO==0)?1:L__INFIFO);
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generate
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generate
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// Either copy the input, register it, or put it through a synchronizer.
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// Either copy the input, register it, or put it through a synchronizer.
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wire s__Rx_sync;
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wire s__Rx_sync;
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if (L__SYNC_LENGTH == 0) begin : gen__no_sync
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if (L__SYNC_LENGTH == 0) begin : gen__no_sync
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assign s__Rx_sync = @INPORT@;
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assign s__Rx_sync = @INPORT@;
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end else if (L__SYNC_LENGTH == 1) begin : gen__short_sync
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end else if (L__SYNC_LENGTH == 1) begin : gen__short_sync
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reg s__Rx_inport_s = 1'b1;
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reg s__Rx_inport_s = 1'b1;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Rx_inport_s <= 1'b1;
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s__Rx_inport_s <= 1'b1;
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else
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else
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s__Rx_inport_s <= @INPORT@;
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s__Rx_inport_s <= @INPORT@;
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assign s__Rx_sync = s__Rx_inport_s;
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assign s__Rx_sync = s__Rx_inport_s;
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end else begin : gen__long_sync
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end else begin : gen__long_sync
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reg [L__SYNC_LENGTH-1:0] s__Rx_inport_s = {(L__SYNC_LENGTH){1'b1}};
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reg [L__SYNC_LENGTH-1:0] s__Rx_inport_s = {(L__SYNC_LENGTH){1'b1}};
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Rx_inport_s <= {(L__SYNC_LENGTH){1'b1}};
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s__Rx_inport_s <= {(L__SYNC_LENGTH){1'b1}};
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else
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else
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s__Rx_inport_s <= { s__Rx_inport_s[0+:L__SYNC_LENGTH-1], @INPORT@ };
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s__Rx_inport_s <= { s__Rx_inport_s[0+:L__SYNC_LENGTH-1], @INPORT@ };
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assign s__Rx_sync = s__Rx_inport_s[L__SYNC_LENGTH-1];
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assign s__Rx_sync = s__Rx_inport_s[L__SYNC_LENGTH-1];
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end
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end
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// Either pass the received signal with no deglitching or apply deglitch
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// Either pass the received signal with no deglitching or apply deglitch
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// hysteresis that consists of not changing the reported state unless all of
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// hysteresis that consists of not changing the reported state unless all of
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// the queued bits have changed state.
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// the queued bits have changed state.
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reg s__Rx_deglitched;
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reg s__Rx_deglitched;
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if (L__DEGLITCH_LENGTH == 0) begin : gen__nodeglitch
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if (L__DEGLITCH_LENGTH == 0) begin : gen__nodeglitch
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always @ (*)
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always @ (*)
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s__Rx_deglitched = s__Rx_sync;
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s__Rx_deglitched = s__Rx_sync;
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end else begin : gen__deglitch
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end else begin : gen__deglitch
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initial s__Rx_deglitched = 1'b1;
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initial s__Rx_deglitched = 1'b1;
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reg [L__DEGLITCH_LENGTH-1:0] s__Rx_deglitch = {(L__DEGLITCH_LENGTH){1'b1}};
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reg [L__DEGLITCH_LENGTH-1:0] s__Rx_deglitch = {(L__DEGLITCH_LENGTH){1'b1}};
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always @ (posedge i_clk) begin
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always @ (posedge i_clk) begin
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s__Rx_deglitched <= (&(s__Rx_deglitch != {(L__DEGLITCH_LENGTH){s__Rx_deglitched}})) ? ~s__Rx_deglitched : s__Rx_deglitched;
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s__Rx_deglitched <= (&(s__Rx_deglitch != {(L__DEGLITCH_LENGTH){s__Rx_deglitched}})) ? ~s__Rx_deglitched : s__Rx_deglitched;
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s__Rx_deglitch <= { s__Rx_deglitch[0+:L__DEGLITCH_LENGTH-1], @INPORT@ };
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s__Rx_deglitch <= { s__Rx_deglitch[0+:L__DEGLITCH_LENGTH-1], @INPORT@ };
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end
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end
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end
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end
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// Identify edges
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// Identify edges
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reg s__Rx_last = 1'b1;
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reg s__Rx_last = 1'b1;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Rx_last <= 1'b1;
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s__Rx_last <= 1'b1;
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else
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else
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s__Rx_last <= s__Rx_deglitched;
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s__Rx_last <= s__Rx_deglitched;
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reg s__Rx_edge = 1'b0;
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reg s__Rx_edge = 1'b0;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Rx_edge <= 1'b0;
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s__Rx_edge <= 1'b0;
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else
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else
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s__Rx_edge <= (s__Rx_deglitched != s__Rx_last);
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s__Rx_edge <= (s__Rx_deglitched != s__Rx_last);
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// Run a timer at twice the desired edge frequency rate. Synchronize it to the
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// Run a timer at twice the desired edge frequency rate. Synchronize it to the
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// incoming edges.
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// incoming edges.
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reg [L__BAUDMETHOD_NBITS-1:0] s__Rx_event_time = L__BAUDMETHOD_MINUS[L__BAUDMETHOD_NBITS-1:0];
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reg [L__BAUDMETHOD_NBITS-1:0] s__Rx_event_time = L__BAUDMETHOD_MINUS[L__BAUDMETHOD_NBITS-1:0];
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reg s__Rx_event_time_msb = L__BAUDMETHOD_MINUS[L__BAUDMETHOD_NBITS-1];
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reg s__Rx_event_time_msb = L__BAUDMETHOD_MINUS[L__BAUDMETHOD_NBITS-1];
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wire s__Rx_event_time_expired = ({s__Rx_event_time_msb,s__Rx_event_time[L__BAUDMETHOD_NBITS-1]} == 2'b01);
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wire s__Rx_event_time_expired = ({s__Rx_event_time_msb,s__Rx_event_time[L__BAUDMETHOD_NBITS-1]} == 2'b01);
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst) begin
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if (i_rst) begin
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s__Rx_event_time <= L__BAUDMETHOD_MINUS[L__BAUDMETHOD_NBITS-1:0];
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s__Rx_event_time <= L__BAUDMETHOD_MINUS[L__BAUDMETHOD_NBITS-1:0];
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s__Rx_event_time_msb <= L__BAUDMETHOD_MINUS[L__BAUDMETHOD_NBITS-1];
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s__Rx_event_time_msb <= L__BAUDMETHOD_MINUS[L__BAUDMETHOD_NBITS-1];
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end else if (s__Rx_edge || s__Rx_event_time_expired) begin
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end else if (s__Rx_edge || s__Rx_event_time_expired) begin
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s__Rx_event_time <= L__BAUDMETHOD_MINUS[L__BAUDMETHOD_NBITS-1:0];
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s__Rx_event_time <= L__BAUDMETHOD_MINUS[L__BAUDMETHOD_NBITS-1:0];
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s__Rx_event_time_msb <= L__BAUDMETHOD_MINUS[L__BAUDMETHOD_NBITS-1];
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s__Rx_event_time_msb <= L__BAUDMETHOD_MINUS[L__BAUDMETHOD_NBITS-1];
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end else begin
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end else begin
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s__Rx_event_time <= s__Rx_event_time - { {(L__BAUDMETHOD_NBITS-1){1'b0}}, 1'b1 };
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s__Rx_event_time <= s__Rx_event_time - { {(L__BAUDMETHOD_NBITS-1){1'b0}}, 1'b1 };
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s__Rx_event_time_msb <= s__Rx_event_time[L__BAUDMETHOD_NBITS-1];
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s__Rx_event_time_msb <= s__Rx_event_time[L__BAUDMETHOD_NBITS-1];
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end
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end
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// Fabricate composite event detection.
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// Fabricate composite event detection.
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reg s__Rx_idle;
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reg s__Rx_idle;
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wire s__Rx_wait_edge;
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wire s__Rx_wait_edge;
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reg s__Rx_event = 1'b0;
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reg s__Rx_event = 1'b0;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Rx_event <= 1'b0;
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s__Rx_event <= 1'b0;
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else
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else
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s__Rx_event <= ~s__Rx_event && ((s__Rx_wait_edge && s__Rx_edge) || (~s__Rx_idle && s__Rx_event_time_expired));
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s__Rx_event <= ~s__Rx_event && ((s__Rx_wait_edge && s__Rx_edge) || (~s__Rx_idle && s__Rx_event_time_expired));
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// State machine -- idle state and event (edge/fabricated-edge and midpoint) counter.
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// State machine -- idle state and event (edge/fabricated-edge and midpoint) counter.
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initial s__Rx_idle = 1'b1;
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initial s__Rx_idle = 1'b1;
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reg [L__EVENT_COUNT_NBITS-1:0] s__Rx_event_count = L__EVENT_COUNT[L__EVENT_COUNT_NBITS-1:0];
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reg [L__EVENT_COUNT_NBITS-1:0] s__Rx_event_count = L__EVENT_COUNT[L__EVENT_COUNT_NBITS-1:0];
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reg s__Rx_event_count_zero = 1'b1;
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reg s__Rx_event_count_zero = 1'b1;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst) begin
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if (i_rst) begin
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s__Rx_event_count <= L__EVENT_COUNT[L__EVENT_COUNT_NBITS-1:0];
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s__Rx_event_count <= L__EVENT_COUNT[L__EVENT_COUNT_NBITS-1:0];
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s__Rx_idle <= 1'b1;
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s__Rx_idle <= 1'b1;
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s__Rx_event_count_zero <= 1'b1;
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s__Rx_event_count_zero <= 1'b1;
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end else begin
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end else begin
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if (s__Rx_idle && s__Rx_event)
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if (s__Rx_idle && s__Rx_event)
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s__Rx_idle <= 1'b0;
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s__Rx_idle <= 1'b0;
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else
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else
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s__Rx_idle <= (s__Rx_event_count_zero) ? 1'b1: s__Rx_idle;
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s__Rx_idle <= (s__Rx_event_count_zero) ? 1'b1: s__Rx_idle;
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if (s__Rx_idle) begin
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if (s__Rx_idle) begin
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s__Rx_event_count <= L__EVENT_COUNT[L__EVENT_COUNT_NBITS-1:0];
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s__Rx_event_count <= L__EVENT_COUNT[L__EVENT_COUNT_NBITS-1:0];
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s__Rx_event_count_zero <= 1'b0;
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s__Rx_event_count_zero <= 1'b0;
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end else if (s__Rx_event) begin
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end else if (s__Rx_event) begin
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s__Rx_event_count <= s__Rx_event_count - { {(L__EVENT_COUNT_NBITS-1){1'b0}}, 1'b1 };
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s__Rx_event_count <= s__Rx_event_count - { {(L__EVENT_COUNT_NBITS-1){1'b0}}, 1'b1 };
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s__Rx_event_count_zero <= (s__Rx_event_count == { {(L__EVENT_COUNT_NBITS-1){1'b0}}, 1'b1 });
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s__Rx_event_count_zero <= (s__Rx_event_count == { {(L__EVENT_COUNT_NBITS-1){1'b0}}, 1'b1 });
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end else begin
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end else begin
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s__Rx_event_count <= s__Rx_event_count;
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s__Rx_event_count <= s__Rx_event_count;
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s__Rx_event_count_zero <= 1'b0;
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s__Rx_event_count_zero <= 1'b0;
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end
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end
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end
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end
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assign s__Rx_wait_edge = s__Rx_idle || (L__EVENT_COUNT[0] ^ s__Rx_event_count[0]);
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assign s__Rx_wait_edge = s__Rx_idle || (L__EVENT_COUNT[0] ^ s__Rx_event_count[0]);
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wire s__Rx_wait_sample = ~s__Rx_wait_edge;
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wire s__Rx_wait_sample = ~s__Rx_wait_edge;
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// Generate a strobe when a new bit is to be recorded.
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// Generate a strobe when a new bit is to be recorded.
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reg s__Rx_got_bit = 1'b0;
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reg s__Rx_got_bit = 1'b0;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Rx_got_bit <= 1'b0;
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s__Rx_got_bit <= 1'b0;
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else
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else
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s__Rx_got_bit <= (~s__Rx_idle && s__Rx_wait_sample && s__Rx_event);
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s__Rx_got_bit <= (~s__Rx_idle && s__Rx_wait_sample && s__Rx_event);
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// Record the received bit stream after edges occur (start bit is always discarded)
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// Record the received bit stream after edges occur (start bit is always discarded)
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reg [L__NRX-1:2] s__Rx_s = {(L__NRX-2){1'b1}};
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reg [L__NRX-1:2] s__Rx_s = {(L__NRX-2){1'b1}};
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Rx_s <= {(L__NRX-2){1'b1}};
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s__Rx_s <= {(L__NRX-2){1'b1}};
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else if (s__Rx_got_bit)
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else if (s__Rx_got_bit)
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s__Rx_s <= { s__Rx_last, s__Rx_s[3+:L__NRX-3] };
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s__Rx_s <= { s__Rx_last, s__Rx_s[3+:L__NRX-3] };
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else
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else
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s__Rx_s <= s__Rx_s;
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s__Rx_s <= s__Rx_s;
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// Generate strobe to write the received byte to the output buffer.
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// Generate strobe to write the received byte to the output buffer.
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reg s__Rx_wr = 1'b0;
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reg s__Rx_wr = 1'b0;
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reg [3:0] s__Rx_count = L__NRX[0+:4] - 4'd1;
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reg [3:0] s__Rx_count = L__NRX[0+:4] - 4'd1;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst) begin
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if (i_rst) begin
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s__Rx_wr <= 1'b0;
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s__Rx_wr <= 1'b0;
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s__Rx_count <= L__NRX[0+:4] - 4'd1;
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s__Rx_count <= L__NRX[0+:4] - 4'd1;
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end else if (s__Rx_idle) begin
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end else if (s__Rx_idle) begin
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s__Rx_wr <= 1'b0;
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s__Rx_wr <= 1'b0;
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s__Rx_count <= L__NRX[0+:4] - 4'd1;
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s__Rx_count <= L__NRX[0+:4] - 4'd1;
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end else if (s__Rx_got_bit) begin
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end else if (s__Rx_got_bit) begin
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s__Rx_wr <= (s__Rx_count == 4'd1);
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s__Rx_wr <= (s__Rx_count == 4'd1);
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s__Rx_count <= s__Rx_count - 4'd1;
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s__Rx_count <= s__Rx_count - 4'd1;
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end else begin
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end else begin
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s__Rx_wr <= 1'b0;
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s__Rx_wr <= 1'b0;
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s__Rx_count <= s__Rx_count;
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s__Rx_count <= s__Rx_count;
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end
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end
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// Optional FIFO
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// Optional FIFO
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@RTR_BEGIN@
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@RTR_BEGIN@
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reg s__rtr = 1'b1;
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reg s__rtrn = 1'b1; // Disable reception until the core is out of reset.
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@RTR_END@
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@RTR_END@
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if (L__INFIFO == 0) begin : gen__nofifo
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if (L__INFIFO == 0) begin : gen__nofifo
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst) begin
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if (i_rst) begin
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s__Rx_empty <= 1'b1;
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s__Rx_empty <= 1'b1;
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s__Rx <= 8'h00;
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s__Rx <= 8'h00;
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end else begin
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end else begin
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if (s__Rx_wr)
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if (s__Rx_wr)
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s__Rx <= s__Rx_s[2+:8];
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s__Rx <= s__Rx_s[2+:8];
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else
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else
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s__Rx <= s__Rx;
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s__Rx <= s__Rx;
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if (s__Rx_wr) begin
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if (s__Rx_wr) begin
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if (s__Rx_rd)
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if (s__Rx_rd)
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s__Rx_empty <= s__Rx_empty;
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s__Rx_empty <= s__Rx_empty;
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else
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else
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s__Rx_empty <= 1'b0;
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s__Rx_empty <= 1'b0;
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end else begin
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end else begin
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if (s__Rx_rd)
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if (s__Rx_rd)
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s__Rx_empty <= 1'b1;
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s__Rx_empty <= 1'b1;
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else
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else
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s__Rx_empty <= s__Rx_empty;
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s__Rx_empty <= s__Rx_empty;
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end
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end
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end
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end
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@RTR_BEGIN@
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@RTR_BEGIN@
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__rtr <= 1'b1;
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s__rtrn <= 1'b1;
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else
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else
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s__rtr <= ~s__Rx_idle;
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s__rtrn <= ~s__Rx_idle;
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@RTR_END@
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@RTR_END@
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end else begin : gen__fifo
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end else begin : gen__fifo
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reg [L__INFIFO_NBITS:0] s__Rx_fifo_addr_in;
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reg [L__INFIFO_NBITS:0] s__Rx_fifo_addr_in;
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reg [L__INFIFO_NBITS:0] s__Rx_fifo_addr_out;
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reg [L__INFIFO_NBITS:0] s__Rx_fifo_addr_out;
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wire s__Rx_shift;
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wire s__Rx_shift;
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reg s__Rx_fifo_has_data = 1'b0;
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reg s__Rx_fifo_has_data = 1'b0;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Rx_fifo_has_data <= 1'b0;
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s__Rx_fifo_has_data <= 1'b0;
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else
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else
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s__Rx_fifo_has_data <= (s__Rx_fifo_addr_out != s__Rx_fifo_addr_in) && !s__Rx_shift;
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s__Rx_fifo_has_data <= (s__Rx_fifo_addr_out != s__Rx_fifo_addr_in) && !s__Rx_shift;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst) begin
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if (i_rst) begin
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s__Rx_empty <= 1'b1;
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s__Rx_empty <= 1'b1;
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end else begin
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end else begin
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case ({ s__Rx_fifo_has_data, s__Rx_empty, s__Rx_rd })
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case ({ s__Rx_fifo_has_data, s__Rx_empty, s__Rx_rd })
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3'b000 : s__Rx_empty <= 1'b0;
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3'b000 : s__Rx_empty <= 1'b0;
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3'b001 : s__Rx_empty <= 1'b1; // good read
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3'b001 : s__Rx_empty <= 1'b1; // good read
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3'b010 : s__Rx_empty <= 1'b1;
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3'b010 : s__Rx_empty <= 1'b1;
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3'b011 : s__Rx_empty <= 1'b1; // bad read
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3'b011 : s__Rx_empty <= 1'b1; // bad read
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3'b100 : s__Rx_empty <= 1'b0;
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3'b100 : s__Rx_empty <= 1'b0;
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3'b101 : s__Rx_empty <= 1'b0; // shift, good read
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3'b101 : s__Rx_empty <= 1'b0; // shift, good read
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3'b110 : s__Rx_empty <= 1'b0; // shift
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3'b110 : s__Rx_empty <= 1'b0; // shift
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3'b111 : s__Rx_empty <= 1'b1; // shift, bad read
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3'b111 : s__Rx_empty <= 1'b1; // shift, bad read
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endcase
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endcase
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end
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end
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assign s__Rx_shift = s__Rx_fifo_has_data && (s__Rx_empty || s__Rx_rd);
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assign s__Rx_shift = s__Rx_fifo_has_data && (s__Rx_empty || s__Rx_rd);
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reg s__Rx_full = 1'b0;
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reg s__Rx_full = 1'b0;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Rx_full <= 1'b0;
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s__Rx_full <= 1'b0;
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else
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else
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s__Rx_full <= (s__Rx_fifo_addr_in == (s__Rx_fifo_addr_out ^ { 1'b1, {(L__INFIFO_NBITS){1'b0}} }));
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s__Rx_full <= (s__Rx_fifo_addr_in == (s__Rx_fifo_addr_out ^ { 1'b1, {(L__INFIFO_NBITS){1'b0}} }));
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reg [7:0] s__Rx_fifo_mem[@INFIFO@-1:0];
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reg [7:0] s__Rx_fifo_mem[L__INFIFO-1:0];
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initial s__Rx_fifo_addr_in = {(L__INFIFO_NBITS+1){1'b0}};
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initial s__Rx_fifo_addr_in = {(L__INFIFO_NBITS+1){1'b0}};
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__Rx_fifo_addr_in <= {(L__INFIFO_NBITS+1){1'b0}};
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s__Rx_fifo_addr_in <= {(L__INFIFO_NBITS+1){1'b0}};
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else if (s__Rx_wr && (!s__Rx_full || s__Rx_shift)) begin
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else if (s__Rx_wr && (!s__Rx_full || s__Rx_shift)) begin
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s__Rx_fifo_addr_in <= s__Rx_fifo_addr_in + { {(L__INFIFO_NBITS){1'b0}}, 1'b1 };
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s__Rx_fifo_addr_in <= s__Rx_fifo_addr_in + { {(L__INFIFO_NBITS){1'b0}}, 1'b1 };
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s__Rx_fifo_mem[s__Rx_fifo_addr_in[0+:L__INFIFO_NBITS]] <= s__Rx_s[2+:8];
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s__Rx_fifo_mem[s__Rx_fifo_addr_in[0+:L__INFIFO_NBITS]] <= s__Rx_s[2+:8];
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end else
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end else
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s__Rx_fifo_addr_in <= s__Rx_fifo_addr_in;
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s__Rx_fifo_addr_in <= s__Rx_fifo_addr_in;
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initial s__Rx_fifo_addr_out = {(L__INFIFO_NBITS+1){1'b0}};
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initial s__Rx_fifo_addr_out = {(L__INFIFO_NBITS+1){1'b0}};
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst) begin
|
if (i_rst) begin
|
s__Rx_fifo_addr_out <= {(L__INFIFO_NBITS+1){1'b0}};
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s__Rx_fifo_addr_out <= {(L__INFIFO_NBITS+1){1'b0}};
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s__Rx <= 8'h00;
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s__Rx <= 8'h00;
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end else if (s__Rx_shift) begin
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end else if (s__Rx_shift) begin
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s__Rx_fifo_addr_out <= s__Rx_fifo_addr_out + { {(L__INFIFO_NBITS){1'b0}}, 1'b1 };
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s__Rx_fifo_addr_out <= s__Rx_fifo_addr_out + { {(L__INFIFO_NBITS){1'b0}}, 1'b1 };
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s__Rx <= s__Rx_fifo_mem[s__Rx_fifo_addr_out[0+:L__INFIFO_NBITS]];
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s__Rx <= s__Rx_fifo_mem[s__Rx_fifo_addr_out[0+:L__INFIFO_NBITS]];
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end else begin
|
end else begin
|
s__Rx_fifo_addr_out <= s__Rx_fifo_addr_out;
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s__Rx_fifo_addr_out <= s__Rx_fifo_addr_out;
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s__Rx <= s__Rx;
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s__Rx <= s__Rx;
|
end
|
end
|
@RTR_BEGIN@
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@RTR_BEGIN@
|
// Isn't ready to receive if the FIFO is full or if the FIFO is almost full
|
// Isn't ready to receive if the FIFO is full or if the FIFO is almost full.
|
// and there is incoming data (i.e., receiver is not idle).
|
reg [L__INFIFO_NBITS:0] s__Rx_used = {(L__INFIFO_NBITS+1){1'b0}};
|
reg s__Rx_idle_s = 1'b0;
|
|
always @ (posedge i_clk)
|
always @ (posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
s__Rx_idle_s <= 1'b0;
|
s__Rx_used <= {(L__INFIFO_NBITS+1){1'b0}};
|
else
|
else
|
s__Rx_idle_s <= s__Rx_idle;
|
s__Rx_used <= s__Rx_fifo_addr_in - s__Rx_fifo_addr_out;
|
reg s__Rx_wr_s = 1'b0;
|
|
always @ (posedge i_clk)
|
always @ (posedge i_clk)
|
if (i_rst)
|
if (i_rst)
|
s__Rx_wr_s <= 1'b0;
|
s__rtrn <= 1'b1;
|
else
|
else
|
s__Rx_wr_s <= s__Rx_wr;
|
s__rtrn <= s__Rx_used[L__INFIFO_NBITS] || &(s__Rx_used[L__INFIFO_NBITS-1:@RTR_FIFO_COMPARE@]);
|
reg s__Rx_busy = 1'b0;
|
|
always @ (posedge i_clk)
|
|
if (i_rst)
|
|
s__Rx_busy <= 1'b0;
|
|
else if ({s__Rx_idle_s, s__Rx_idle} == 2'b10)
|
|
s__Rx_busy <= 1'b1;
|
|
else if (s__Rx_wr_s)
|
|
s__Rx_busy <= 1'b0;
|
|
else
|
|
s__Rx_busy <= s__Rx_busy;
|
|
reg s__Rx_almost_full = 1'b0;
|
|
always @ (posedge i_clk)
|
|
if (i_rst)
|
|
s__Rx_almost_full <= 1'b0;
|
|
else
|
|
s__Rx_almost_full <= (s__Rx_fifo_addr_in == (s__Rx_fifo_addr_out + { 1'b0, {(L__INFIFO_NBITS){1'b1}} }));
|
|
always @ (posedge i_clk)
|
|
if (i_rst)
|
|
s__rtr <= 1'b1;
|
|
else
|
|
// s__rtr <= ~(s__Rx_full || (s__Rx_almost_full && ~s__Rx_idle));
|
|
s__rtr <= ~(s__Rx_full || (s__Rx_almost_full && s__Rx_busy));
|
|
@RTR_END@
|
@RTR_END@
|
end
|
end
|
@RTR_BEGIN@
|
@RTR_BEGIN@
|
always @ (*)
|
always @ (*)
|
@RTR_SIGNAL@ <= @RTR_INVERT@s__rtr;
|
@RTR_SIGNAL@ = @RTRN_INVERT@s__rtrn;
|
@RTR_END@
|
@RTR_END@
|
endgenerate
|
endgenerate
|
|
|
